From f05f7726b760d4e9fbaca1c3d5a21cb47ce35b19 Mon Sep 17 00:00:00 2001 From: Jack Koenig Date: Wed, 14 Oct 2020 10:40:06 -0700 Subject: [PATCH] Workaround Chisel 3.4 naming bug --- src/main/scala/devices/debug/Periphery.scala | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/main/scala/devices/debug/Periphery.scala b/src/main/scala/devices/debug/Periphery.scala index c4dadfa45b2..da2e3819fb6 100644 --- a/src/main/scala/devices/debug/Periphery.scala +++ b/src/main/scala/devices/debug/Periphery.scala @@ -3,7 +3,7 @@ package freechips.rocketchip.devices.debug import chisel3._ -import chisel3.experimental.IntParam +import chisel3.experimental.{IntParam, noPrefix} import chisel3.util._ import chisel3.util.HasBlackBoxResource import freechips.rocketchip.config.{Field, Parameters} @@ -109,7 +109,8 @@ trait HasPeripheryDebugModuleImp extends LazyModuleImp { resetctrl } - val debug = outer.debugOpt.map { outerdebug => + // noPrefix is workaround https://github.com/freechipsproject/chisel3/issues/1603 + val debug = noPrefix(outer.debugOpt.map { outerdebug => val debug = IO(new DebugIO) require(!(debug.clockeddmi.isDefined && debug.systemjtag.isDefined), @@ -145,7 +146,7 @@ trait HasPeripheryDebugModuleImp extends LazyModuleImp { outerdebug.module.io.ctrl.debugUnavail.foreach { _ := false.B } debug - } + }) val dtm = debug.flatMap(_.systemjtag.map(instantiateJtagDTM(_)))