-
Notifications
You must be signed in to change notification settings - Fork 9
/
Copy pathiprlib.h
3239 lines (2889 loc) · 80.7 KB
/
iprlib.h
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
#ifndef iprlib_h
#define iprlib_h
/**
* IBM IPR adapter utility library
*
* (C) Copyright 2000, 2004
* International Business Machines Corporation and others.
* All Rights Reserved. This program and the accompanying
* materials are made available under the terms of the
* Common Public License v1.0 which accompanies this distribution.
*
*/
/*
* $Header: /cvsroot/iprdd/iprutils/iprlib.h,v 1.107 2009/06/30 23:32:40 wboyer Exp $
*/
#include <stdarg.h>
#include <stddef.h>
#include <stdio.h>
#include <stdint.h>
#include <fcntl.h>
#include <errno.h>
#include <sys/mount.h>
#include <sys/utsname.h>
#include <linux/types.h>
#include <linux/kdev_t.h>
#include <scsi/scsi.h>
#include <scsi/scsi_ioctl.h>
#include <scsi/sg.h>
#include <sys/ioctl.h>
#include <string.h>
#include <unistd.h>
#include <stdlib.h>
#include <signal.h>
#include <sys/file.h>
#include <dirent.h>
#include <sys/stat.h>
#include <sys/types.h>
#include <sys/socket.h>
#include <sys/wait.h>
#include <ctype.h>
#include <syslog.h>
#include <term.h>
#include <stdbool.h>
#include <netinet/in.h>
#include <asm/byteorder.h>
#include <sys/mman.h>
#include <paths.h>
#include <linux/netlink.h>
#include <time.h>
#include <limits.h>
#include <zlib.h>
#include <sys/param.h>
typedef uint8_t u8;
typedef uint16_t u16;
typedef uint32_t u32;
typedef uint64_t u64;
#define IPR_DASD_UCODE_USRLIB 0
#define IPR_DASD_UCODE_ETC 1
#define IPR_DASD_UCODE_NOT_FOUND -1
#define IPR_DASD_UCODE_NO_HDR 1
#define IPR_DASD_UCODE_HDR 2
#define UCODE_BASE_DIR "/usr/lib/microcode"
#define LINUX_UCODE_BASE_DIR "/lib/firmware"
#define FIRMWARE_HOTPLUG_DIR_TAG "FIRMWARE_DIR"
#define FIRMWARE_HOTPLUG_CONFIG_FILE "/etc/hotplug/firmware.agent"
#define FIRMWARE_HOTPLUG_DEFAULT_DIR LINUX_UCODE_BASE_DIR
#define IPRDUMP_DIR "/var/log/"
#define IPR_JBOD_BLOCK_SIZE 512
#define IPR_DEFAULT_AF_BLOCK_SIZE 522
#define IPR_JBOD_4K_BLOCK_SIZE 4096
#define IPR_AF_4K_BLOCK_SIZE 4224
#define IOCTL_BUFFER_SIZE 512
#define IPR_MAX_NUM_BUSES 4
#define IPR_VENDOR_ID_LEN 8
#define IPR_PROD_ID_LEN 16
#define IPR_SERIAL_NUM_LEN 8
#define ESM_SERIAL_NUM_LEN 12
#define YL_SERIAL_NUM_LEN 12
#define IPR_DESCRIPTION_LEN 16
#define IPR_VPD_PLANT_CODE_LEN 4
#define IPR_VPD_CACHE_SIZE_LEN 3
#define IPR_VPD_DRAM_SIZE_LEN 3
#define IPR_VPD_PART_NUM_LEN 12
#define IPR_CCB_CDB_LEN 16
#define IPR_QAC_BUFFER_SIZE 200000
#define IPR_SIS32_QAC_BUFFER_SIZE 16000
#define IPR_INVALID_ARRAY_ID 0xFF
#define IPR_IOA_RESOURCE_HANDLE 0xffffffff
#define IPR_RECLAIM_NUM_BLOCKS_MULTIPLIER 256
#define IPR_SDB_CHECK_AND_QUIESCE 0x00
#define IPR_SDB_CHECK_ONLY 0x40
#define IPR_SDB_CHECK_AND_QUIESCE_ENC 0x0e
#define IPR_RDB_UNQUIESCE_AND_REBALANCE 0x20
#define IPR_MAX_NUM_SUPP_INQ_PAGES 36
#define SES_MAX_NUM_SUPP_INQ_PAGES 7
#define IPR_DUMP_TRACE_ENTRY_SIZE 8192
#define IPR_MODE_SENSE_LENGTH 255
#define IPR_DEFECT_LIST_HDR_LEN 4
#define IPR_FORMAT_DATA 0x10
#define IPR_FORMAT_IMMED 2
#define IPR_ARRAY_CMD_TIMEOUT (2 * 60) /* 2 minutes */
#define IPR_INTERNAL_DEV_TIMEOUT (2 * 60) /* 2 minutes */
#define IPR_FORMAT_UNIT_TIMEOUT (3 * 60 * 60) /* 3 hours */
#define IPR_INTERNAL_TIMEOUT (30) /* 30 seconds */
#define IPR_SUSPEND_DEV_BUS_TIMEOUT (35) /* 35 seconds */
#define IPR_EVALUATE_DEVICE_TIMEOUT (2 * 60) /* 2 minutes */
#define IPR_WRITE_BUFFER_TIMEOUT (8 * 60) /* 8 minutes */
#define IPR_CACHE_RECLAIM_TIMEOUT (10 * 60) /* 10 minutes */
#define SET_DASD_TIMEOUTS_TIMEOUT (2 * 60)
#define IPR_NUM_DRIVE_ELEM_STATUS_ENTRIES 50
#define IPR_DRIVE_ELEM_STATUS_EMPTY 5
#define IPR_DRIVE_ELEM_STATUS_POPULATED 1
#define IPR_DRIVE_ELEM_STATUS_UNSUPP 0
#define IPR_DRIVE_ELEM_STATUS_NO_ACCESS 8
#define IPR_TIMEOUT_SECOND_RADIX 0x0000
#define IPR_TIMEOUT_MINUTE_RADIX 0x4000
#define IPR_TIMEOUT_RADIX_MASK 0xC000
#define IPR_TIMEOUT_RADIX_IS_MINUTE(to) \
(((to) & IPR_TIMEOUT_RADIX_MASK) == IPR_TIMEOUT_MINUTE_RADIX)
#define IPR_TIMEOUT_RADIX_IS_SECONDS(to) \
(((to) & IPR_TIMEOUT_RADIX_MASK) == IPR_TIMEOUT_SECOND_RADIX)
#define IPR_TIMEOUT_MASK 0x3FFF
#define IPR_IOA_DEBUG 0xDDu
#define IPR_IOA_DEBUG_READ_IOA_MEM 0x00u
#define IPR_IOA_DEBUG_WRITE_IOA_MEM 0x01u
#define IPR_IOA_DEBUG_READ_FLIT 0x03u
#define IPR_IOA_DEBUG_ENABLE_DBG_FUNC 0x0Au
#define IPR_IOA_DEBUG_DISABLE_DBG_FUNC 0x0Bu
#define IPR_STD_INQ_Z0_TERM_LEN 8
#define IPR_STD_INQ_Z1_TERM_LEN 12
#define IPR_STD_INQ_Z2_TERM_LEN 4
#define IPR_STD_INQ_Z3_TERM_LEN 5
#define IPR_STD_INQ_Z4_TERM_LEN 4
#define IPR_STD_INQ_Z5_TERM_LEN 2
#define IPR_STD_INQ_Z6_TERM_LEN 10
#define IPR_STD_INQ_PART_NUM_LEN 12
#define IPR_STD_INQ_EC_LEVEL_LEN 10
#define IPR_STD_INQ_FRU_NUM_LEN 12
#define IPR_START_STOP_STOP 0x00
#define IPR_START_STOP_START 0x01
#define IPR_READ_CAPACITY_16 0x10
#define IPR_SERVICE_ACTION_IN 0x9E
#define IPR_MAINTENANCE_IN 0xA3
#define IPR_QUERY_MULTI_ADAPTER_STATUS 0x01
#define IPR_MAINTENANCE_OUT 0xA4
#define IPR_CHANGE_MULTI_ADAPTER_ASSIGNMENT 0x02
#define IPR_QUERY_RESOURCE_STATE 0xC2
#define IPR_QUERY_COMMAND_STATUS 0xCB
#define IPR_SUSPEND_DEV_BUS 0xC8
#define IPR_RESUME_DEV_BUS 0xC9
#define IPR_IOA_SERVICE_ACTION 0xD2
#define IPR_QUERY_RES_ADDR_ALIASES 0x10
#define IPR_QUERY_RES_PATH_ALIASES 0x20
#define IPR_DISRUPT_DEVICE 0x11
#define IPR_QUERY_SAS_EXPANDER_INFO 0x12
#define IPR_QUERY_RES_REDUNDANCY_INFO 0x13
#define IPR_QUERY_RES_REDUNDANCY_INFO64 0x23
#define IPR_CHANGE_CACHE_PARAMETERS 0x14
#define IPR_QUERY_CACHE_PARAMETERS 0x16
#define IPR_LIVE_DUMP 0x31
#define IPR_QUERY_IOA_DEV_PORT 0x32
#define IPR_EVALUATE_DEVICE 0xE4
#define SKIP_READ 0xE8
#define SKIP_WRITE 0xEA
#define QUERY_DASD_TIMEOUTS 0xEB
#define SET_DASD_TIMEOUTS 0xEC
#define IPR_MIGRATE_ARRAY_PROTECTION 0xEF
#define IPR_QUERY_ARRAY_CONFIG 0xF0
#define IPR_START_ARRAY_PROTECTION 0xF1
#define IPR_STOP_ARRAY_PROTECTION 0xF2
#define IPR_RESYNC_ARRAY_PROTECTION 0xF3
#define IPR_ADD_ARRAY_DEVICE 0xF4
#define IPR_REMOVE_ARRAY_DEVICE 0xF5
#define IPR_REBUILD_DEVICE_DATA 0xF6
#define IPR_RECLAIM_CACHE_STORE 0xF8
#define IPR_SET_ARRAY_ASYMMETRIC_ACCESS 0xFA
#define IPR_RECLAIM_ACTION 0x68
#define IPR_RECLAIM_PERFORM 0x00
#define IPR_RECLAIM_RESET_BATTERY_ERROR 0x08
#define IPR_RECLAIM_EXTENDED_INFO 0x10
#define IPR_RECLAIM_QUERY 0x20
#define IPR_RECLAIM_RESET 0x40
#define IPR_RECLAIM_FORCE_BATTERY_ERROR 0x60
#define IPR_RECLAIM_UNKNOWN_PERM 0x80
#define SET_SUPPORTED_DEVICES 0xFB
#define IPR_STD_INQUIRY 0xFF
#ifndef REPORT_LUNS
#define REPORT_LUNS 0xA0
#endif
#define IPR_XLATE_DEV_FMT_RC(rc) ((((rc) & 127) == 51) ? -EIO : 0)
#define IPR_TYPE_AF_DISK 0xC
#define IPR_TYPE_ADAPTER 0x1f
#define IPR_TYPE_ARRAY 0x1f
#define IPR_TYPE_EMPTY_SLOT 0xff
#define IPR_ACTIVE_OPTIMIZED 0x0
#define IPR_ACTIVE_NON_OPTIMIZED 0x1
#define IPR_ACTIVE_STANDBY 0x2
#define IPR_CLEAR_ASYMMETRIC_STATE 0x0
#define IPR_PRESERVE_ASYMMETRIC_STATE 0x80
#define IPR_IOA_CACHING_DUAL_FAILURE_DISABLED 0x0
#define IPR_IOA_CACHING_DUAL_FAILURE_ENABLED 0x1
#define IPR_IOA_REQUESTED_CACHING_DEFAULT 0x0
#define IPR_IOA_REQUESTED_CACHING_DISABLED 0x1
#define IPR_IOA_CACHING_DEFAULT_DUAL_ENABLED 0x2
#define IPR_IOA_CACHING_DISABLED_DUAL_ENABLED 0x3
#define IPR_IOA_VSET_CACHE_ENABLED 0x4
#define IPR_IOA_SET_CACHING_DEFAULT 0x0
#define IPR_IOA_SET_CACHING_DISABLED 0x10
#define IPR_IOA_SET_CACHING_DUAL_DISABLED 0x20
#define IPR_IOA_SET_CACHING_DUAL_ENABLED 0x30
#define IPR_IOA_SET_VSET_CACHE_ENABLED 0x40
#define IPR_IOA_SET_VSET_CACHE_DISABLED 0x50
#define PHYSICAL_LOCATION_LENGTH 1024
#define IPR_HDD 0x0
#define IPR_SSD 0x1
#define IPR_BLK_DEV_CLASS_4K 0x4
#define IPR_RI 0x1
#define IPR_ARRAY_VIRTUAL_BUS 0x1
#define IPR_VSET_VIRTUAL_BUS 0x2
#define IPR_IOAFP_VIRTUAL_BUS 0x3
#define IPR_SAS_STD_INQ_UCODE_ID 12
#define IPR_SAS_STD_INQ_VENDOR_UNIQ 40
#define IPR_SAS_STD_INQ_PLANT_MAN 4
#define IPR_SAS_STD_INQ_DATE_MAN 5
#define IPR_SAS_STD_INQ_FRU_COUNT 4
#define IPR_SAS_STD_INQ_FRU_FIELD_LEN 2
#define IPR_SAS_STD_INQ_FRU_PN 12
#define IPR_SAS_STD_INQ_ASM_EC_LVL 10
#define IPR_SAS_STD_INQ_ASM_PART_NUM 12
#define IPR_SAS_STD_INQ_FRU_ASM_EC 10
#define IPR_SAS_INQ_BYTES_WARRANTY_LEN 3
/* Device write cache policies. */
enum {IPR_DEV_CACHE_WRITE_THROUGH = 0, IPR_DEV_CACHE_WRITE_BACK};
/* System P Operating modes */
enum system_p_mode {POWER_VM, POWER_KVM, POWER_BAREMETAL} ;
#define IPR_IS_DASD_DEVICE(std_inq_data) \
((((std_inq_data).peri_dev_type) == TYPE_DISK) && !((std_inq_data).removeable_medium))
#define IPR_SET_MODE(change_mask, cur_val, new_val) \
{ \
int mod_bits = (cur_val ^ new_val); \
if ((change_mask & mod_bits) == mod_bits) \
{ \
cur_val = new_val; \
} \
}
#define ARRAY_SIZE(x) (sizeof(x)/sizeof((x)[0]))
#define IPR_RECORD_ID_SUPPORTED_ARRAYS __constant_be16_to_cpu((u16)0)
#define IPR_RECORD_ID_COMP_RECORD __constant_be16_to_cpu((u16)3)
#define IPR_RECORD_ID_ARRAY_RECORD __constant_be16_to_cpu((u16)4)
#define IPR_RECORD_ID_DEVICE_RECORD __constant_be16_to_cpu((u16)5)
#define IPR_RECORD_ID_ARRAY_RECORD_3 __constant_be16_to_cpu((u16)6)
#define IPR_RECORD_ID_VSET_RECORD_3 __constant_be16_to_cpu((u16)7)
#define IPR_RECORD_ID_DEVICE_RECORD_3 __constant_be16_to_cpu((u16)8)
extern struct ipr_array_query_data *ipr_array_query_data;
extern int num_ioas;
extern struct ipr_ioa *ipr_ioa_head;
extern struct ipr_ioa *ipr_ioa_tail;
extern int runtime;
extern void (*exit_func) (void);
extern int daemonize;
extern int ipr_debug;
extern int ipr_force;
extern int ipr_sg_required;
extern int polling_mode;
extern int ipr_fast;
extern int format_done;
extern char *tool_name;
extern struct sysfs_dev *head_zdev;
extern struct sysfs_dev *tail_zdev;
extern enum system_p_mode power_cur_mode;
extern int tool_init_retry;
struct sysfs_dev {
u64 device_id;
char ioa_pci_addr[16];
struct sysfs_dev *next, *prev;
};
struct ipr_phy {
#if defined (__BIG_ENDIAN_BITFIELD)
u8 box:3;
u8 phy:5;
#elif defined (__LITTLE_ENDIAN_BITFIELD)
u8 phy:5;
u8 box:3;
#endif
};
struct ipr_phy_2bit_hop {
#if defined (__BIG_ENDIAN_BITFIELD)
u8 box:2;
u8 phy:6;
#elif defined (__LITTLE_ENDIAN_BITFIELD)
u8 phy:6;
u8 box:2;
#endif
};
struct ipr_res_addr {
u8 host;
u8 bus;
union {
u8 target;
struct ipr_phy phy;
struct ipr_phy_2bit_hop phy_2bit_hop;
};
u8 lun;
#define IPR_GET_PHYSICAL_LOCATOR(res_addr) \
(((res_addr)->bus << 16) | ((res_addr)->target << 8) | (res_addr)->lun)
};
struct ipr_res_path {
u8 res_path_bytes[8];
};
struct ipr_std_inq_vpids {
u8 vendor_id[IPR_VENDOR_ID_LEN]; /* Vendor ID */
u8 product_id[IPR_PROD_ID_LEN]; /* Product ID */
};
struct ipr_common_record {
u16 record_id;
u16 record_len;
};
struct ipr_vset_res_state {
u16 stripe_size;
u8 prot_level;
u8 num_devices_in_vset;
u32 reserved6;
u32 ilid;
u32 failing_dev_ioasc;
struct ipr_res_addr failing_dev_res_addr;
u32 failing_dev_res_handle;
u8 prot_level_str[8];
};
struct ipr_dasd_res_state {
u32 data_path_width; /* bits */
u32 data_xfer_rate; /* 100 KBytes/second */
u32 ilid;
u32 failing_dev_ioasc;
struct ipr_res_addr failing_dev_res_addr;
u32 failing_dev_res_handle;
};
struct ipr_gscsi_res_state {
u32 data_path_width; /* bits */
u32 data_xfer_rate; /* 100 KBytes/second */
};
struct ipr_supported_device {
u16 data_length;
u8 reserved;
u8 num_records;
struct ipr_std_inq_vpids vpids;
u8 reserved2[16];
};
struct ipr_mode_page_hdr {
#if defined (__BIG_ENDIAN_BITFIELD)
u8 parms_saveable:1;
u8 reserved1:1;
u8 page_code:6;
#elif defined (__LITTLE_ENDIAN_BITFIELD)
u8 page_code:6;
u8 reserved1:1;
u8 parms_saveable:1;
#endif
u8 page_length;
};
struct ipr_vendor_mode_page {
/* Mode page 0x00 */
struct ipr_mode_page_hdr hdr;
#if defined (__BIG_ENDIAN_BITFIELD)
u8 qpe:1;
u8 uqe:1;
u8 dwd:1;
u8 reserved1:4;
u8 arhes:1;
#elif defined (__LITTLE_ENDIAN_BITFIELD)
u8 arhes:1;
u8 reserved1:4;
u8 dwd:1;
u8 uqe:1;
u8 qpe:1;
#endif
#if defined (__BIG_ENDIAN_BITFIELD)
u8 asdpe:1;
u8 reserved2:1;
u8 cmdac:1;
u8 rpfae:1;
u8 dotf:1;
u8 reserved3:1;
u8 rrnde:1;
u8 cpe:1;
#elif defined (__LITTLE_ENDIAN_BITFIELD)
u8 cpe:1;
u8 rrnde:1;
u8 reserved3:1;
u8 dotf:1;
u8 rpfae:1;
u8 cmdac:1;
u8 reserved2:1;
u8 asdpe:1;
#endif
#if defined (__BIG_ENDIAN_BITFIELD)
u8 reserved4:6;
u8 dwlro:1;
u8 dlro:1;
#elif defined (__LITTLE_ENDIAN_BITFIELD)
u8 dlro:1;
u8 dwlro:1;
u8 reserved4:6;
#endif
#if defined (__BIG_ENDIAN_BITFIELD)
u8 reserved5:2;
u8 dsn:1;
u8 frdd:1;
u8 dpsdp:1;
u8 wpen:1;
u8 caen:1;
u8 ovple:1;
#elif defined (__LITTLE_ENDIAN_BITFIELD)
u8 ovple:1;
u8 caen:1;
u8 wpen:1;
u8 dpsdp:1;
u8 frdd:1;
u8 dsn:1;
u8 reserved5:2;
#endif
u8 reserved7[2];
#if defined (__BIG_ENDIAN_BITFIELD)
u8 reserved8:1;
u8 adc:1;
u8 qemc:1;
u8 drd:1;
u8 led_mode:4;
#elif defined (__LITTLE_ENDIAN_BITFIELD)
u8 led_mode:4;
u8 drd:1;
u8 qemc:1;
u8 adc:1;
u8 reserved8:1;
#endif
u8 temp_threshold;
u8 cmd_aging_limit_hi;
u8 cmd_aging_limit_lo;
u8 qpe_read_threshold;
u8 reserved10;
#if defined (__BIG_ENDIAN_BITFIELD)
u8 drrt:1;
u8 dnr:1;
u8 reserved11:1;
u8 rarr:1;
u8 ffmt:1;
u8 reserved12:3;
#elif defined (__LITTLE_ENDIAN_BITFIELD)
u8 reserved12:3;
u8 ffmt:1;
u8 rarr:1;
u8 reserved11:1;
u8 dnr:1;
u8 drrt:1;
#endif
#if defined (__BIG_ENDIAN_BITFIELD)
u8 rtp:1;
u8 rrc:1;
u8 fcert:1;
u8 reserved13:1;
u8 drpdv:1;
u8 dsf:1;
u8 irt:1;
u8 ivr:1;
#elif defined (__LITTLE_ENDIAN_BITFIELD)
u8 ivr:1;
u8 irt:1;
u8 dsf:1;
u8 drpdv:1;
u8 reserved13:1;
u8 fcert:1;
u8 rrc:1;
u8 rtp:1;
#endif
};
struct ipr_caching_parameters_page {
/* Mode page 0x08 */
struct ipr_mode_page_hdr hdr;
#if defined (__BIG_ENDIAN_BITFIELD)
u8 ic:1;
u8 abpf:1;
u8 cap:1;
u8 disc:1;
u8 size:1;
u8 wce:1;
u8 mf:1;
u8 rcd:1;
#elif defined (__LITTLE_ENDIAN_BITFIELD)
u8 rcd:1;
u8 mf:1;
u8 wce:1;
u8 size:1;
u8 disc:1;
u8 cap:1;
u8 abpf:1;
u8 ic:1;
#endif
#if defined (__BIG_ENDIAN_BITFIELD)
u8 demand_read_retention_priority:4;
u8 write_retention_priority:4;
#elif defined (__LITTLE_ENDIAN_BITFIELD)
u8 write_retention_priority:4;
u8 demand_read_retention_priority:4;
#endif
u16 disable_prefetch_transfer_length;
u16 minimum_prefetch;
u16 maximum_prefetch;
u16 maximum_prefetch_ceiling;
#if defined (__BIG_ENDIAN_BITFIELD)
u8 fsw:1;
u8 lbcss:1;
u8 dra:1;
u8 reserved:5;
#elif defined (__LITTLE_ENDIAN_BITFIELD)
u8 reserved:5;
u8 dra:1;
u8 lbcss:1;
u8 fsw:1;
#endif
u8 cache_segments;
u16 cache_segment_size;
u8 reserved1;
u8 non_cache_segment_size[3];
};
struct ipr_control_mode_page {
/* Mode page 0x0A */
struct ipr_mode_page_hdr hdr;
#if defined (__BIG_ENDIAN_BITFIELD)
u8 tst:3;
u8 reserved1:3;
u8 gltsd:1;
u8 rlec:1;
u8 queue_algorithm_modifier:4;
u8 reserved2:1;
u8 qerr:2;
u8 dque:1;
u8 reserved3:1;
u8 rac:1;
u8 reserved4:2;
u8 swp:1;
u8 raerp:1;
u8 uaaerp:1;
u8 eaerp:1;
u8 ato:1;
u8 tas:1;
u8 reserved5:3;
u8 autoload_mode:3;
#elif defined (__LITTLE_ENDIAN_BITFIELD)
u8 rlec:1;
u8 gltsd:1;
u8 reserved1:3;
u8 tst:3;
u8 dque:1;
u8 qerr:2;
u8 reserved2:1;
u8 queue_algorithm_modifier:4;
u8 eaerp:1;
u8 uaaerp:1;
u8 raerp:1;
u8 swp:1;
u8 reserved4:2;
u8 rac:1;
u8 reserved3:1;
u8 autoload_mode:3;
u8 reserved5:3;
u8 tas:1;
u8 ato:1;
#endif
u16 ready_aen_holdoff_period;
u16 busy_timeout_period;
u16 reserved6;
};
struct ipr_rw_err_mode_page {
/* Page code 0x01 */
struct ipr_mode_page_hdr hdr;
#if defined (__BIG_ENDIAN_BITFIELD)
u8 awre:1;
u8 arre:1;
u8 tb:1;
u8 rc:1;
u8 eer:1;
u8 per:1;
u8 dte:1;
u8 dcr:1;
#elif defined (__LITTLE_ENDIAN_BITFIELD)
u8 dcr:1;
u8 dte:1;
u8 per:1;
u8 eer:1;
u8 rc:1;
u8 tb:1;
u8 arre:1;
u8 awre:1;
#endif
u8 read_retry_count;
u8 correction_span;
u8 head_offset_count;
u8 data_strobe_offset_count;
u8 reserved1;
u8 write_retry_count;
u8 reserved2;
u16 recovery_time_limit;
};
struct ipr_reclaim_query_data {
u8 action_status;
#define IPR_ACTION_SUCCESSFUL 0
#define IPR_ACTION_NOT_REQUIRED 1
#define IPR_ACTION_NOT_PERFORMED 2
#if defined (__BIG_ENDIAN_BITFIELD)
u8 reclaim_known_needed:1;
u8 reclaim_unknown_needed:1;
u8 reserved2:2;
u8 reclaim_known_performed:1;
u8 reclaim_unknown_performed:1;
u8 reserved3:1;
u8 num_blocks_needs_multiplier:1;
#elif defined (__LITTLE_ENDIAN_BITFIELD)
u8 num_blocks_needs_multiplier:1;
u8 reserved3:1;
u8 reclaim_unknown_performed:1;
u8 reclaim_known_performed:1;
u8 reserved2:2;
u8 reclaim_unknown_needed:1;
u8 reclaim_known_needed:1;
#endif
u16 num_blocks;
u8 rechargeable_battery_type;
#define IPR_BATTERY_TYPE_NO_BATTERY 0
#define IPR_BATTERY_TYPE_NICD 1
#define IPR_BATTERY_TYPE_NIMH 2
#define IPR_BATTERY_TYPE_LIION 3
u8 rechargeable_battery_error_state;
#define IPR_BATTERY_NO_ERROR_STATE 0
#define IPR_BATTERY_WARNING_STATE 1
#define IPR_BATTERY_ERROR_STATE 2
#if defined (__BIG_ENDIAN_BITFIELD)
u8 conc_maint_battery:1;
u8 battery_replace_allowed:1;
u8 reserved4:6;
#elif defined (__LITTLE_ENDIAN_BITFIELD)
u8 reserved4:6;
u8 battery_replace_allowed:1;
u8 conc_maint_battery:1;
#endif
u8 reserved5;
u16 raw_power_on_time;
u16 adjusted_power_on_time;
u16 estimated_time_to_battery_warning;
u16 estimated_time_to_battery_failure;
u8 reserved6[240];
};
struct ipr_sdt_entry {
u32 bar_str_offset;
u32 end_offset;
u8 entry_byte;
u8 reserved[3];
#if defined (__BIG_ENDIAN_BITFIELD)
u8 endian:1;
u8 reserved1:1;
u8 valid_entry:1;
u8 reserved2:5;
#elif defined (__LITTLE_ENDIAN_BITFIELD)
u8 reserved2:5;
u8 valid_entry:1;
u8 reserved1:1;
u8 endian:1;
#endif
u8 resv;
u16 priority;
};
struct ipr_query_res_state {
#if defined (__BIG_ENDIAN_BITFIELD)
u8 reserved1:1;
u8 not_oper:1;
u8 not_ready:1;
u8 not_func:1;
u8 reserved2:4;
u8 read_write_prot:1;
u8 reserved3:7;
u8 prot_dev_failed:1;
u8 prot_suspended:1;
u8 prot_resuming:1;
u8 degraded_oper:1;
u8 service_req:1;
u8 reserved4:3;
#elif defined (__LITTLE_ENDIAN_BITFIELD)
u8 reserved2:4;
u8 not_func:1;
u8 not_ready:1;
u8 not_oper:1;
u8 reserved1:1;
u8 reserved3:7;
u8 read_write_prot:1;
u8 reserved4:3;
u8 service_req:1;
u8 degraded_oper:1;
u8 prot_resuming:1;
u8 prot_suspended:1;
u8 prot_dev_failed:1;
#endif
u8 reserved5;
union {
struct ipr_vset_res_state vset;
struct ipr_dasd_res_state dasd;
struct ipr_gscsi_res_state gscsi;
};
};
struct ipr_query_io_port {
u32 length;
#define IOA_DEV_PORT_ACTIVE 0x0
#define IOA_DEV_PORT_SUSPEND 0x1
#define IOA_DEV_PORT_PARTIAL_SUSPEND 0x2
#define IOA_DEV_PORT_UNKNOWN 0xFF
u8 port_state;
u8 reserved1;
u8 reserved2;
u8 reserved3;
};
struct ipr_res_addr_aliases {
u32 length;
struct ipr_res_addr res_addr[10];
};
#define for_each_ra_alias(ra, aliases) \
for (ra = (aliases)->res_addr; \
ra < ((aliases)->res_addr + (ntohl((aliases)->length) / sizeof(struct ipr_res_addr))) && \
ra < ((aliases)->res_addr + ARRAY_SIZE((aliases)->res_addr)); \
ra++)
struct ipr_res_path_aliases {
u32 length;
u32 reserved1;
struct ipr_res_path res_path[10];
};
#define for_each_rp_alias(rp, aliases) \
for (rp = (aliases)->res_path; \
rp < ((aliases)->res_path + ((ntohl((aliases)->length)- 4) / sizeof(struct ipr_res_path))) && \
rp < ((aliases)->res_path + ARRAY_SIZE((aliases)->res_path)); \
rp++)
struct ipr_array_cap_entry {
u8 prot_level;
#define IPR_DEFAULT_RAID_LVL "5"
#if defined (__BIG_ENDIAN_BITFIELD)
u8 include_allowed:1;
u8 reserved:5;
u8 format_overlay_type:2;
#elif defined (__LITTLE_ENDIAN_BITFIELD)
u8 format_overlay_type:2;
u8 reserved:5;
u8 include_allowed:1;
#endif
#define IPR_FORMAT_ADD_DEVICES 1
#define IPR_FORMAT_REMOVE_DEVICES 2
u16 reserved2;
u8 reserved3;
u8 max_num_array_devices;
u8 min_num_array_devices;
u8 min_mult_array_devices;
u8 min_num_per_tier;
u8 reserved4;
u16 supported_stripe_sizes;
u16 reserved5;
u16 recommended_stripe_size;
u8 prot_level_str[8];
};
#define for_each_cap_entry(cap, supp) \
for (cap = (supp)->entry; \
(unsigned long)cap < ((unsigned long)((supp)->entry) + (ntohs((supp)->num_entries) * ntohs((supp)->entry_length))); \
cap = (struct ipr_array_cap_entry *)((unsigned long)cap + ntohs((supp)->entry_length)))
struct ipr_array_record {
struct ipr_common_record common;
#if defined (__BIG_ENDIAN_BITFIELD)
u8 issue_cmd:1;
u8 known_zeroed:1;
u8 reserved1:6;
#elif defined (__LITTLE_ENDIAN_BITFIELD)
u8 reserved1:6;
u8 known_zeroed:1;
u8 issue_cmd:1;
#endif
#if defined (__BIG_ENDIAN_BITFIELD)
u8 saved_asym_access_state:4;
u8 current_asym_access_state:4;
#elif defined (__LITTLE_ENDIAN_BITFIELD)
u8 current_asym_access_state:4;
u8 saved_asym_access_state:4;
#endif
#if defined (__BIG_ENDIAN_BITFIELD)
u8 established:1;
u8 exposed:1;
u8 non_func:1;
u8 high_avail:1;
u8 no_config_entry:1;
u8 reserved3:3;
u8 start_cand:1;
u8 stop_cand:1;
u8 resync_cand:1;
u8 migrate_cand:1;
u8 asym_access_cand:1;
u8 reserved4:3;
#elif defined (__LITTLE_ENDIAN_BITFIELD)
u8 reserved3:3;
u8 no_config_entry:1;
u8 high_avail:1;
u8 non_func:1;
u8 exposed:1;
u8 established:1;
u8 reserved4:3;
u8 asym_access_cand:1;
u8 migrate_cand:1;
u8 resync_cand:1;
u8 stop_cand:1;
u8 start_cand:1;
#endif
union {
struct {
u16 stripe_size;
u8 raid_level;
u8 array_id;
u32 resource_handle;
struct ipr_res_addr resource_addr;
struct ipr_res_addr last_resource_addr;
u8 vendor_id[IPR_VENDOR_ID_LEN];
u8 product_id[IPR_PROD_ID_LEN];
u8 serial_number[8];
#if defined (__BIG_ENDIAN_BITFIELD)
u8 block_dev_class:3;
u8 reserved51:1;
u8 read_intensive:1;
u8 reserved5:3;
#elif defined (__LITTLE_ENDIAN_BITFIELD)
u8 reserved5:3;
u8 read_intensive:1;
u8 reserved51:1;
u8 block_dev_class:3;
#endif
u8 reserved6;
u8 reserved7;
u8 reserved8;
}__attribute__((packed, aligned (4))) type2;
struct {
u8 reserved5;
u8 raid_level;
u16 stripe_size;
u8 reserved6[4];
u8 reserved7[16];
u8 last_func_res_path[8];
u8 reserved8[2];
u8 array_id;
#if defined (__BIG_ENDIAN_BITFIELD)
u8 block_dev_class:3;
u8 reserved91:1;
u8 read_intensive:1;
u8 reserved9:3;
#elif defined (__LITTLE_ENDIAN_BITFIELD)
u8 reserved9:3;
u8 read_intensive:1;
u8 reserved91:1;
u8 block_dev_class:3;
#endif
u32 resource_handle;
u8 dev_id[8];
u8 lun[8];
u8 wwn[16];
u8 res_path[8];
u8 vendor_id[IPR_VENDOR_ID_LEN];
u8 product_id[IPR_PROD_ID_LEN];
u8 serial_number[IPR_SERIAL_NUM_LEN];
u8 desc[IPR_DESCRIPTION_LEN];
u8 total_arr_size[8];
u8 total_size_inuse[8];
u8 max_size_to_use[8];
u8 total_size_enc[8];
u8 total_inuse_enc[8];
u8 max_size_enc[8];
}__attribute__((packed, aligned (4))) type3;
};
}__attribute__((packed, aligned (4)));
struct ipr_dev_record {
struct ipr_common_record common;
#if defined (__BIG_ENDIAN_BITFIELD)
u8 issue_cmd:1;
u8 known_zeroed:1;
u8 reserved:6;
#elif defined (__LITTLE_ENDIAN_BITFIELD)
u8 reserved:6;
u8 known_zeroed:1;
u8 issue_cmd:1;
#endif
#if defined (__BIG_ENDIAN_BITFIELD)
u8 saved_asym_access_state:4;
u8 current_asym_access_state:4;
#elif defined (__LITTLE_ENDIAN_BITFIELD)
u8 current_asym_access_state:4;
u8 saved_asym_access_state:4;
#endif
#if defined (__BIG_ENDIAN_BITFIELD)
u8 array_member:1;
u8 has_parity:1;
u8 is_exposed_device:1;
u8 is_hot_spare:1;
u8 no_cfgte_vol:1;
u8 no_cfgte_dev:1;
u8 reserved2:2;
u8 start_cand:1;
u8 parity_cand:1;
u8 stop_cand:1;
u8 resync_cand:1;