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| 1 | +/* |
| 2 | + cpu_map_atmega2560.h - CPU and pin mapping configuration file |
| 3 | + Part of Grbl |
| 4 | +
|
| 5 | + Copyright (c) 2012-2015 Sungeun K. Jeon |
| 6 | +
|
| 7 | + Grbl is free software: you can redistribute it and/or modify |
| 8 | + it under the terms of the GNU General Public License as published by |
| 9 | + the Free Software Foundation, either version 3 of the License, or |
| 10 | + (at your option) any later version. |
| 11 | +
|
| 12 | + Grbl is distributed in the hope that it will be useful, |
| 13 | + but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | + GNU General Public License for more details. |
| 16 | +
|
| 17 | + You should have received a copy of the GNU General Public License |
| 18 | + along with Grbl. If not, see <http://www.gnu.org/licenses/>. |
| 19 | +*/ |
| 20 | + |
| 21 | +/* This cpu_map file serves as a central pin mapping settings file for AVR Mega 2560 */ |
| 22 | + |
| 23 | + |
| 24 | +#ifdef GRBL_PLATFORM |
| 25 | +#error "cpu_map already defined: GRBL_PLATFORM=" GRBL_PLATFORM |
| 26 | +#endif |
| 27 | + |
| 28 | + |
| 29 | +#define GRBL_PLATFORM "Atmega2560" |
| 30 | + |
| 31 | +// Serial port pins |
| 32 | +#define SERIAL_RX USART0_RX_vect |
| 33 | +#define SERIAL_UDRE USART0_UDRE_vect |
| 34 | + |
| 35 | +// Increase Buffers to make use of extra SRAM |
| 36 | +//#define RX_BUFFER_SIZE 256 |
| 37 | +//#define TX_BUFFER_SIZE 128 |
| 38 | +//#define BLOCK_BUFFER_SIZE 36 |
| 39 | +//#define LINE_BUFFER_SIZE 100 |
| 40 | + |
| 41 | +// Define step pulse output pins. NOTE: All step bit pins must be on the same port. |
| 42 | +#define STEP_DDR DDRA |
| 43 | +#define STEP_PORT PORTA |
| 44 | +#define STEP_PIN PINA |
| 45 | +#define X_STEP_BIT 2 // MEGA2560 Digital Pin 24 |
| 46 | +#define Y_STEP_BIT 3 // MEGA2560 Digital Pin 25 |
| 47 | +#define Z_STEP_BIT 4 // MEGA2560 Digital Pin 26 |
| 48 | +#define STEP_MASK ((1<<X_STEP_BIT)|(1<<Y_STEP_BIT)|(1<<Z_STEP_BIT)) // All step bits |
| 49 | + |
| 50 | +// Define step direction output pins. NOTE: All direction pins must be on the same port. |
| 51 | +#define DIRECTION_DDR DDRC |
| 52 | +#define DIRECTION_PORT PORTC |
| 53 | +#define DIRECTION_PIN PINC |
| 54 | +#define X_DIRECTION_BIT 7 // MEGA2560 Digital Pin 30 |
| 55 | +#define Y_DIRECTION_BIT 6 // MEGA2560 Digital Pin 31 |
| 56 | +#define Z_DIRECTION_BIT 5 // MEGA2560 Digital Pin 32 |
| 57 | +#define DIRECTION_MASK ((1<<X_DIRECTION_BIT)|(1<<Y_DIRECTION_BIT)|(1<<Z_DIRECTION_BIT)) // All direction bits |
| 58 | + |
| 59 | +// Define stepper driver enable/disable output pin. |
| 60 | +#define STEPPERS_DISABLE_DDR DDRB |
| 61 | +#define STEPPERS_DISABLE_PORT PORTB |
| 62 | +#define STEPPERS_DISABLE_BIT 7 // MEGA2560 Digital Pin 13 |
| 63 | +#define STEPPERS_DISABLE_MASK (1<<STEPPERS_DISABLE_BIT) |
| 64 | + |
| 65 | +// Define homing/hard limit switch input pins and limit interrupt vectors. |
| 66 | +// NOTE: All limit bit pins must be on the same port |
| 67 | +#define LIMIT_DDR DDRB |
| 68 | +#define LIMIT_PORT PORTB |
| 69 | +#define LIMIT_PIN PINB |
| 70 | +#define X_LIMIT_BIT 4 // MEGA2560 Digital Pin 10 |
| 71 | +#define Y_LIMIT_BIT 5 // MEGA2560 Digital Pin 11 |
| 72 | +#define Z_LIMIT_BIT 6 // MEGA2560 Digital Pin 12 |
| 73 | +#define LIMIT_INT PCIE0 // Pin change interrupt enable pin |
| 74 | +#define LIMIT_INT_vect PCINT0_vect |
| 75 | +#define LIMIT_PCMSK PCMSK0 // Pin change interrupt register |
| 76 | +#define LIMIT_MASK ((1<<X_LIMIT_BIT)|(1<<Y_LIMIT_BIT)|(1<<Z_LIMIT_BIT)) // All limit bits |
| 77 | + |
| 78 | +// Define spindle enable and spindle direction output pins. |
| 79 | +#define SPINDLE_ENABLE_DDR DDRH |
| 80 | +#define SPINDLE_ENABLE_PORT PORTH |
| 81 | +#define SPINDLE_ENABLE_BIT 3 // MEGA2560 Digital Pin 6 |
| 82 | +#define SPINDLE_DIRECTION_DDR DDRE |
| 83 | +#define SPINDLE_DIRECTION_PORT PORTE |
| 84 | +#define SPINDLE_DIRECTION_BIT 3 // MEGA2560 Digital Pin 5 |
| 85 | + |
| 86 | +// Define flood and mist coolant enable output pins. |
| 87 | +// NOTE: Uno analog pins 4 and 5 are reserved for an i2c interface, and may be installed at |
| 88 | +// a later date if flash and memory space allows. |
| 89 | +#define COOLANT_FLOOD_DDR DDRH |
| 90 | +#define COOLANT_FLOOD_PORT PORTH |
| 91 | +#define COOLANT_FLOOD_BIT 5 // MEGA2560 Digital Pin 8 |
| 92 | +#ifdef ENABLE_M7 // Mist coolant disabled by default. See config.h to enable/disable. |
| 93 | +#define COOLANT_MIST_DDR DDRH |
| 94 | +#define COOLANT_MIST_PORT PORTH |
| 95 | +#define COOLANT_MIST_BIT 6 // MEGA2560 Digital Pin 9 |
| 96 | +#endif |
| 97 | + |
| 98 | +// Define user-control CONTROLs (cycle start, reset, feed hold) input pins. |
| 99 | +// NOTE: All CONTROLs pins must be on the same port and not on a port with other input pins (limits). |
| 100 | +#define CONTROL_DDR DDRK |
| 101 | +#define CONTROL_PIN PINK |
| 102 | +#define CONTROL_PORT PORTK |
| 103 | +#define RESET_BIT 0 // MEGA2560 Analog Pin 8 |
| 104 | +#define FEED_HOLD_BIT 1 // MEGA2560 Analog Pin 9 |
| 105 | +#define CYCLE_START_BIT 2 // MEGA2560 Analog Pin 10 |
| 106 | +#define SAFETY_DOOR_BIT 3 // MEGA2560 Analog Pin 11 |
| 107 | +#define CONTROL_INT PCIE2 // Pin change interrupt enable pin |
| 108 | +#define CONTROL_INT_vect PCINT2_vect |
| 109 | +#define CONTROL_PCMSK PCMSK2 // Pin change interrupt register |
| 110 | +#define CONTROL_MASK ((1<<RESET_BIT)|(1<<FEED_HOLD_BIT)|(1<<CYCLE_START_BIT)|(1<<SAFETY_DOOR_BIT)) |
| 111 | + |
| 112 | +// Define probe switch input pin. |
| 113 | +#define PROBE_DDR DDRK |
| 114 | +#define PROBE_PIN PINK |
| 115 | +#define PROBE_PORT PORTK |
| 116 | +#define PROBE_BIT 7 // MEGA2560 Analog Pin 15 |
| 117 | +#define PROBE_MASK (1<<PROBE_BIT) |
| 118 | + |
| 119 | +// Start of PWM & Stepper Enabled Spindle |
| 120 | +#ifdef VARIABLE_SPINDLE |
| 121 | + // Advanced Configuration Below You should not need to touch these variables |
| 122 | + // Set Timer up to use TIMER4B which is attached to Digital Pin 7 |
| 123 | + #define PWM_MAX_VALUE 65535.0 |
| 124 | + #define TCCRA_REGISTER TCCR4A |
| 125 | + #define TCCRB_REGISTER TCCR4B |
| 126 | + #define OCR_REGISTER OCR4B |
| 127 | + |
| 128 | + #define COMB_BIT COM4B1 |
| 129 | + #define WAVE0_REGISTER WGM40 |
| 130 | + #define WAVE1_REGISTER WGM41 |
| 131 | + #define WAVE2_REGISTER WGM42 |
| 132 | + #define WAVE3_REGISTER WGM43 |
| 133 | + |
| 134 | + #define SPINDLE_PWM_DDR DDRH |
| 135 | + #define SPINDLE_PWM_PORT PORTH |
| 136 | + #define SPINDLE_PWM_BIT 4 // MEGA2560 Digital Pin 97 |
| 137 | +#endif // End of VARIABLE_SPINDLE |
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