Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Experiments with Small Devices #25

Open
antoinecarme opened this issue Oct 23, 2020 · 7 comments
Open

Experiments with Small Devices #25

antoinecarme opened this issue Oct 23, 2020 · 7 comments

Comments

@antoinecarme
Copy link
Member

antoinecarme commented Oct 23, 2020

ml2cpp, as it is now, allows converting any ML model to a C++ code for inference purposes.

This code is however not yet optimized to run on small devices : these devices may have low CPU speed, low memory, low-power, no FPU, no real OS. ml2cpp Jupyter notebooks were run and inference was tested on a sparc64 or x86-64 server with gigabytes of memory and running full-featured g++ compiler.

We need:

  1. get some hardware/micro-controller : STM32, ESP32 and K210 (riscv-64) at least.
  2. Check that the generated code can be compiled with the respective gcc versions (C++-17 support, exceptions, RTTI are not always available).
  3. check the capacities of these devices (CPU + memory)
  4. Check floating point issues : is there an FPU? half-precision floats (float16), bfloat16, ...
  5. get an emulator for each device (qemu-???). use it for automated tests.

Priority 1 : Getting at least one of these devices running all these steps (feasibility). choose the one with less constraints (K210 can run a small linux)

The goal is to be able to run the model on the bare metal. No arduino. No MicroPython.

Using STM32, ESP32 or K210 is here only for tuning purposes. Their only added value is to provide a test envoironment so that C++ code will be incrementally adapted in a real-world case.

@antoinecarme
Copy link
Member Author

STM32 + ESP32 + K210 (from left to right)

image

@antoinecarme
Copy link
Member Author

@antoinecarme
Copy link
Member Author

antoinecarme commented Jan 6, 2022

SiFive, a pioneer of the RISC-V free and open source instruction set architecture (ISA), has announced the fruit of its work with ArchiTek Corporation: AiOnIc, an edge AI processor that combines SiFive's E3-series RISC-V cores with ArchiTek's Intelligence Pixel Engine (aIPE).

To be tested (when available) :

https://www.hackster.io/news/sifive-architek-announce-high-efficiency-sub-1w-edge-ai-processor-the-aionic-1d8aa537f77f

image

@antoinecarme
Copy link
Member Author

antoinecarme commented Jan 6, 2022

Kendryte K510 Edge AI Chip as a Triple-Core RISC-V Part with 3 TOPS NPU. Has FP16 support

To be tested (when available) :

https://canaan.io/product/kendryte-k510

image

@antoinecarme
Copy link
Member Author

antoinecarme commented Jan 6, 2022

Alibaba On The Bleeding Edge Of RISC-V With XT910. Has FP16 support.

To be tested (when available) :

https://www.nextplatform.com/2020/08/21/alibaba-on-the-bleeding-edge-of-risc-v-with-xt910/

image

image

@antoinecarme
Copy link
Member Author

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

No branches or pull requests

1 participant