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Experiments with Small Devices #25
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SiFive, a pioneer of the RISC-V free and open source instruction set architecture (ISA), has announced the fruit of its work with ArchiTek Corporation: AiOnIc, an edge AI processor that combines SiFive's E3-series RISC-V cores with ArchiTek's Intelligence Pixel Engine (aIPE). To be tested (when available) : |
Kendryte K510 Edge AI Chip as a Triple-Core RISC-V Part with 3 TOPS NPU. Has FP16 support To be tested (when available) : |
Alibaba On The Bleeding Edge Of RISC-V With XT910. Has FP16 support. To be tested (when available) : https://www.nextplatform.com/2020/08/21/alibaba-on-the-bleeding-edge-of-risc-v-with-xt910/ |
ml2cpp, as it is now, allows converting any ML model to a C++ code for inference purposes.
This code is however not yet optimized to run on small devices : these devices may have low CPU speed, low memory, low-power, no FPU, no real OS. ml2cpp Jupyter notebooks were run and inference was tested on a sparc64 or x86-64 server with gigabytes of memory and running full-featured g++ compiler.
We need:
Priority 1 : Getting at least one of these devices running all these steps (feasibility). choose the one with less constraints (K210 can run a small linux)
The goal is to be able to run the model on the bare metal.
No arduino.No MicroPython.Using STM32, ESP32 or K210 is here only for tuning purposes. Their only added value is to provide a test envoironment so that C++ code will be incrementally adapted in a real-world case.
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