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Forth debugger: add missing disass
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‎forth/disass.py

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# Opcodes
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# for each, we store the mnemonic and mode id (see 'modes' dict below)
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opcodes = {
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0: [ 'brk' , 9 ], # brk s
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1: [ 'ora' , 11 ], # ora (zp,x)
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4: [ 'tsb' , 10 ], # tsb zp
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5: [ 'ora' , 10 ], # ora zp
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6: [ 'asl' , 10 ], # asl zp
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7: [ 'rmb0', 10 ], # rmb0 zp
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8: [ 'php' , 9 ], # php s
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9: [ 'ora' , 6 ], # ora #
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10: [ 'asl' , 5 ], # asl A
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12: [ 'tsb' , 0 ], # tsb a
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13: [ 'ora' , 0 ], # ora a
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14: [ 'asl' , 0 ], # asl a
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15: [ 'bbr0', 8 ], # bbr0 r
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16: [ 'bpl' , 8 ], # bpl r
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17: [ 'ora' , 15 ], # ora (zp),y
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18: [ 'ora' , 14 ], # ora (zp)
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20: [ 'trb' , 10 ], # trb zp
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21: [ 'ora' , 12 ], # ora zp,x
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22: [ 'asl' , 12 ], # asl zp,x
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23: [ 'rmb1', 10 ], # rmb1 zp
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24: [ 'clc' , 7 ], # clc i
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25: [ 'ora' , 3 ], # ora a,y
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26: [ 'inc' , 5 ], # inc A
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28: [ 'trb' , 0 ], # trb a
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29: [ 'ora' , 2 ], # ora a,x
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30: [ 'asl' , 2 ], # asl a,x
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31: [ 'bbr1', 8 ], # bbr1 r
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32: [ 'jsr' , 0 ], # jsr a
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33: [ 'and' , 11 ], # and (zp,x)
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36: [ 'bit' , 10 ], # bit zp
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37: [ 'and' , 10 ], # and zp
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38: [ 'rol' , 10 ], # rol zp
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39: [ 'rmb2', 10 ], # rmb2 zp
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40: [ 'plp' , 9 ], # plp s
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41: [ 'and' , 6 ], # and #
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42: [ 'rol' , 5 ], # rol A
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44: [ 'bit' , 0 ], # bit a
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45: [ 'and' , 0 ], # and a
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46: [ 'rol' , 0 ], # rol a
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47: [ 'bbr2', 8 ], # bbr2 r
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48: [ 'bmi' , 8 ], # bmi r
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49: [ 'and' , 15 ], # and (zp),y
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50: [ 'and' , 14 ], # and (zp)
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52: [ 'bit' , 12 ], # bit zp,x
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53: [ 'and' , 12 ], # and zp,x
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54: [ 'rol' , 12 ], # rol zp,x
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55: [ 'rmb3', 10 ], # rmb3 zp
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56: [ 'sec' , 7 ], # sec i
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57: [ 'and' , 3 ], # and a,y
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58: [ 'dec' , 5 ], # dec A
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60: [ 'bit' , 2 ], # bit a,x
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61: [ 'and' , 2 ], # and a,x
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62: [ 'rol' , 2 ], # rol a,x
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63: [ 'bbr3', 8 ], # bbr3 r
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64: [ 'rti' , 9 ], # rti s
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65: [ 'eor' , 11 ], # eor (zp,x)
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69: [ 'eor' , 10 ], # eor zp
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70: [ 'lsr' , 10 ], # lsr zp
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71: [ 'rmb4', 10 ], # rmb4 zp
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72: [ 'pha' , 9 ], # pha s
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73: [ 'eor' , 6 ], # eor #
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74: [ 'lsr' , 5 ], # lsr A
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76: [ 'jmp' , 0 ], # jmp a
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77: [ 'eor' , 0 ], # eor a
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78: [ 'lsr' , 0 ], # lsr a
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79: [ 'bbr4', 8 ], # bbr4 r
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80: [ 'bvc' , 8 ], # bvc r
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81: [ 'eor' , 15 ], # eor (zp),y
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82: [ 'eor' , 14 ], # eor (zp)
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85: [ 'eor' , 12 ], # eor zp,x
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86: [ 'lsr' , 12 ], # lsr zp,x
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87: [ 'rmb5', 10 ], # rmb5 zp
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88: [ 'cli' , 7 ], # cli i
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89: [ 'eor' , 3 ], # eor a,y
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90: [ 'phy' , 9 ], # phy s
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93: [ 'eor' , 2 ], # eor a,x
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94: [ 'lsr' , 2 ], # lsr a,x
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95: [ 'bbr5', 8 ], # bbr5 r
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96: [ 'rts' , 9 ], # rts s
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97: [ 'adc' , 11 ], # adc (zp,x)
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100: [ 'stz' , 10 ], # stz zp
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101: [ 'adc' , 10 ], # adc zp
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102: [ 'ror' , 10 ], # ror zp
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103: [ 'rmb6', 10 ], # rmb6 zp
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104: [ 'pla' , 9 ], # pla s
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105: [ 'adc' , 6 ], # adc #
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106: [ 'ror' , 5 ], # ror A
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108: [ 'jmp' , 4 ], # jmp (a)
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109: [ 'adc' , 0 ], # adc a
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110: [ 'ror' , 0 ], # ror a
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111: [ 'bbr6', 8 ], # bbr6 r
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112: [ 'bvs' , 8 ], # bvs r
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113: [ 'adc' , 15 ], # adc (zp),y
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114: [ 'adc' , 14 ], # adc (zp)
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116: [ 'stz' , 12 ], # stz zp,x
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117: [ 'adc' , 12 ], # adc zp,x
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118: [ 'ror' , 12 ], # ror zp,x
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119: [ 'rmb7', 10 ], # rmb7 zp
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120: [ 'sei' , 7 ], # sei i
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121: [ 'adc' , 3 ], # adc a,y
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122: [ 'ply' , 9 ], # ply s
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124: [ 'jmp' , 1 ], # jmp (a,x)
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125: [ 'adc' , 2 ], # adc a,x
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126: [ 'ror' , 2 ], # ror a,x
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127: [ 'bbr7', 8 ], # bbr7 r
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128: [ 'bra' , 8 ], # bra r
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129: [ 'sta' , 11 ], # sta (zp,x)
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132: [ 'sty' , 10 ], # sty zp
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133: [ 'sta' , 10 ], # sta zp
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134: [ 'stx' , 10 ], # stx zp
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135: [ 'smb0', 10 ], # smb0 zp
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136: [ 'dey' , 7 ], # dey i
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137: [ 'bit' , 6 ], # bit #
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138: [ 'txa' , 7 ], # txa i
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140: [ 'sty' , 0 ], # sty a
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141: [ 'sta' , 0 ], # sta a
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142: [ 'stx' , 0 ], # stx a
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143: [ 'bbs0', 8 ], # bbs0 r
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144: [ 'bcc' , 8 ], # bcc r
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145: [ 'sta' , 15 ], # sta (zp),y
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146: [ 'sta' , 14 ], # sta (zp)
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148: [ 'sty' , 12 ], # sty zp,x
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149: [ 'sta' , 12 ], # sta zp,x
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150: [ 'stx' , 13 ], # stx zp,y
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151: [ 'smb1', 10 ], # smb1 zp
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152: [ 'tya' , 7 ], # tya i
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153: [ 'sta' , 3 ], # sta a,y
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154: [ 'txs' , 7 ], # txs i
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156: [ 'stz' , 0 ], # stz a
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157: [ 'sta' , 2 ], # sta a,x
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158: [ 'stz' , 2 ], # stz a,x
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159: [ 'bbs1', 8 ], # bbs1 r
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160: [ 'ldy' , 6 ], # ldy #
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161: [ 'lda' , 11 ], # lda (zp,x)
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162: [ 'ldx' , 6 ], # ldx #
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164: [ 'ldy' , 10 ], # ldy zp
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165: [ 'lda' , 10 ], # lda zp
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166: [ 'ldx' , 10 ], # ldx zp
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167: [ 'smb2', 10 ], # smb2 zp
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168: [ 'tay' , 7 ], # tay i
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169: [ 'lda' , 6 ], # lda #
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170: [ 'tax' , 7 ], # tax i
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172: [ 'ldy' , 0 ], # ldy a
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173: [ 'lda' , 0 ], # lda a
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174: [ 'ldx' , 0 ], # ldx a
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175: [ 'bbs2', 8 ], # bbs2 r
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176: [ 'bcs' , 8 ], # bcs r
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177: [ 'lda' , 15 ], # lda (zp),y
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178: [ 'lda' , 14 ], # lda (zp)
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180: [ 'ldy' , 12 ], # ldy zp,x
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181: [ 'lda' , 12 ], # lda zp,x
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182: [ 'ldx' , 13 ], # ldx zp,y
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183: [ 'smb3', 10 ], # smb3 zp
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184: [ 'clv' , 7 ], # clv i
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185: [ 'lda' , 3 ], # lda a,y
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186: [ 'tsx' , 7 ], # tsx i
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188: [ 'ldy' , 2 ], # ldy a,x
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189: [ 'lda' , 2 ], # lda a,x
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190: [ 'ldx' , 3 ], # ldx a,y
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191: [ 'bbs3', 8 ], # bbs3 r
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192: [ 'cpy' , 6 ], # cpy #
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193: [ 'cmp' , 11 ], # cmp (zp,x)
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196: [ 'cpy' , 10 ], # cpy zp
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197: [ 'cmp' , 10 ], # cmp zp
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198: [ 'dec' , 10 ], # dec zp
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199: [ 'smb4', 10 ], # smb4 zp
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200: [ 'iny' , 7 ], # iny i
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201: [ 'cmp' , 6 ], # cmp #
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202: [ 'dex' , 7 ], # dex i
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203: [ 'wai' , 7 ], # wai i
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204: [ 'cpy' , 0 ], # cpy a
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205: [ 'cmp' , 0 ], # cmp a
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206: [ 'dec' , 0 ], # dec a
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207: [ 'bbs4', 8 ], # bbs4 r
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208: [ 'bne' , 8 ], # bne r
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209: [ 'cmp' , 15 ], # cmp (zp),y
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210: [ 'cmp' , 14 ], # cmp (zp)
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213: [ 'cmp' , 12 ], # cmp zp,x
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214: [ 'dec' , 12 ], # dec zp,x
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215: [ 'smb5', 10 ], # smb5 zp
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216: [ 'cld' , 7 ], # cld i
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217: [ 'cmp' , 3 ], # cmp a,y
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218: [ 'phx' , 9 ], # phx s
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219: [ 'stp' , 7 ], # stp i
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221: [ 'cmp' , 2 ], # cmp a,x
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222: [ 'dec' , 2 ], # dec a,x
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223: [ 'bbs5', 8 ], # bbs5 r
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224: [ 'cpx' , 6 ], # cpx #
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225: [ 'sbc' , 11 ], # sbc (zp,x)
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228: [ 'cpx' , 10 ], # cpx zp
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229: [ 'sbc' , 10 ], # sbc zp
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230: [ 'inc' , 10 ], # inc zp
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231: [ 'smb6', 10 ], # smb6 zp
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232: [ 'inx' , 7 ], # inx i
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233: [ 'sbc' , 6 ], # sbc #
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234: [ 'nop' , 7 ], # nop i
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236: [ 'cpx' , 0 ], # cpx a
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237: [ 'sbc' , 0 ], # sbc a
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238: [ 'inc' , 0 ], # inc a
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239: [ 'bbs6', 8 ], # bbs6 r
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240: [ 'beq' , 8 ], # beq r
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241: [ 'sbc' , 15 ], # sbc (zp),y
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242: [ 'sbc' , 14 ], # sbc (zp)
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245: [ 'sbc' , 12 ], # sbc zp,x
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246: [ 'inc' , 12 ], # inc zp,x
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247: [ 'smb7', 10 ], # smb7 zp
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248: [ 'sed' , 7 ], # sed i
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249: [ 'sbc' , 3 ], # sbc a,y
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250: [ 'plx' , 9 ], # plx s
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253: [ 'sbc' , 2 ], # sbc a,x
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254: [ 'inc' , 2 ], # inc a,x
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255: [ 'bbs7', 8 ], # bbs7 r
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}
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# Addressing modes
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# for each, we store the mode name and instructions length
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modes = {
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0: [ 'a', 3 ],
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1: [ '(a,x)', 3 ],
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2: [ 'a,x', 3 ],
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3: [ 'a,y', 3 ],
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4: [ '(a)', 3 ],
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5: [ 'A', 1 ],
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6: [ '#', 2 ],
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7: [ 'i', 1 ],
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8: [ 'r', 2 ],
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9: [ 's', 1 ],
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10: [ 'zp', 2 ],
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11: [ '(zp,x)', 2 ],
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12: [ 'zp,x', 2 ],
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13: [ 'zp,y', 2 ],
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14: [ '(zp)', 2 ],
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15: [ '(zp),y', 2 ],
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}
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def isValidOpcode(b):
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return b in opcodes.keys()
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# decode an opcode byte b
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# returns mnemonic, mode, length
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def decode(b):
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if isinstance(b,str):
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b=hex2dec(b)
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if isValidOpcode(b):
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o, m = opcodes[b]
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m, l = modes[m]
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return o, m, l
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else:
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return None,None,None
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def hex2dec(s):
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return int(s,16)
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def render_instr(_args):
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# args is a list: addr, mnemonic, [op1, op2]
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# addr: the instruction's address. int or hex str
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# mnemonic, op1 & op2 are strings in hex
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# we create a copy of the _args list, because we will modify it
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args=_args[:]
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# we revers the list, so we can pop each item
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# and at the end, the operand's byte are correctly ordered
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addr = args.pop(0)
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if isinstance(addr,str):
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addr=hex2dec(addr)
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opcode = args.pop(0)
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# if isinstance(opcode,str):
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# opcode=hex2dec(opcode)
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comment = ""
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unknown = ".."
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o,m,l = decode(opcode)
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miss = 0
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while True:
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miss = l - len(args) - 1 # how many operands bytes we are missing
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if miss >= 0:
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break
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# too much args, remove
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args.pop()
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args.reverse()
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operand="".join(args)
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args.reverse() # now we need it again in the chronological order, for hexdump
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operand = unknown*miss + operand
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hexdump = " ".join( [opcode] + args + [ unknown for _ in range(miss) ])
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#if o.startswith("b") and o not in ["bit", "brk"] :
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if m == "r" :
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if miss==0 :
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dest = addr + 2
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operand = hex2dec(operand)
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if operand > 0x7f:
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dest -= 0x100 - operand
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else:
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dest += operand
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operand = "%04X" % dest
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else:
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# add an extra unknown byte
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operand = unknown + operand
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if l>1:
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operand = "$"+operand
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if m == "#":
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operand = "#"+operand
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if ',x' in m:
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operand += ",x"
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if m.startswith('('):
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operand = "(" + operand + ")"
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if m.endswith('y'):
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operand += ",y"
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if m == "A":
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operand = "A"
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# return ("%04X: %-10s %s %-8s %-4s %s " % (addr, hexdump.upper(), o, operand, m, comment))
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return ("%04X: %s %-8s " % (addr, o, operand))

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