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‎docs/GPI.md

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The Qualcomm Generic Peripheral Interface (or GPI) is a middle man firmware sitting between the HWIO/FIFO direct memory access Qualcomm Universal Peripheral (QUP) interfaces, and a client, in order to support greater security permissions as well as simultaneous access from multiple clients (HLOS, DSPs etc).
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## Bus Summary
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SM8150 Contains 4 QUPs, with the following SEs available for each:
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---
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QUPv3 South:
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| Si | QUP | SE | Address | Length | IRQ | Android DT Names |
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|----------------|------|----|------------|------------|-----|------------------------------|
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| QUPV3_WRAP0_S0 | QUP0 | 0 | 0x00880000 | 0x00004000 | 601 | qupv3_se0_i2c, qupv3_se0_spi |
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| QUPV3_WRAP0_S1 | QUP0 | 1 | 0x00884000 | 0x00004000 | 602 | qupv3_se1_i2c, qupv3_se1_spi |
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| QUPV3_WRAP0_S2 | QUP0 | 2 | 0x00888000 | 0x00004000 | 603 | qupv3_se2_i2c, qupv3_se2_spi |
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| QUPV3_WRAP0_S3 | QUP0 | 3 | 0x0088C000 | 0x00004000 | 604 | qupv3_se3_i2c, qupv3_se3_spi |
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| QUPV3_WRAP0_S4 | QUP0 | 4 | 0x00890000 | 0x00004000 | 605 | qupv3_se4_i2c, qupv3_se4_spi |
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| QUPV3_WRAP0_S5 | QUP0 | 5 | 0x00894000 | 0x00004000 | 606 | qupv3_se5_i2c, qupv3_se5_spi |
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| QUPV3_WRAP0_S6 | QUP0 | 6 | 0x00898000 | 0x00004000 | 607 | qupv3_se6_i2c, qupv3_se6_spi |
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| QUPV3_WRAP0_S7 | QUP0 | 7 | 0x0089C000 | 0x00004000 | 608 | qupv3_se7_i2c, qupv3_se7_spi |
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---
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QUPv3 North:
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| Si | QUP | SE | Address | Length | IRQ | Android DT Names |
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|----------------|------|----|------------|------------|-----|--------------------------------------------------|
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| QUPV3_WRAP1_S0 | QUP1 | 8 | 0x00A80000 | 0x00004000 | 353 | qupv3_se8_i2c, qupv3_se8_spi |
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| QUPV3_WRAP1_S1 | QUP1 | 9 | 0x00A84000 | 0x00004000 | 354 | qupv3_se4_2uart, qupv3_se9_i2c, qupv3_se9_spi |
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| QUPV3_WRAP1_S2 | QUP1 | 10 | 0x00A88000 | 0x00004000 | 355 | qupv3_se10_i2c, qupv3_se10_spi |
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| QUPV3_WRAP1_S3 | QUP1 | 11 | 0x00A8C000 | 0x00004000 | 356 | qupv3_se11_i2c, qupv3_se11_spi |
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| QUPV3_WRAP1_S4 | QUP1 | 12 | 0x00A90000 | 0x00004000 | 357 | qupv3_se12_2uart, qupv3_se12_i2c, qupv3_se12_spi |
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| QUPV3_WRAP1_S5 | QUP1 | 16 | 0x00A94000 | 0x00004000 | 358 | qupv3_se16_i2c, qupv3_se16_spi |
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---
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QUPv3 East:
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| Si | QUP | SE | Address | Length | IRQ | Android DT Names |
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|----------------|------|----|------------|------------|-----|--------------------------------------------------|
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| QUPV3_WRAP2_S0 | QUP2 | 17 | 0x00C80000 | 0x00004000 | 373 | qupv3_se17_i2c, qupv3_se17_spi |
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| QUPV3_WRAP2_S1 | QUP2 | 18 | 0x00C84000 | 0x00004000 | 583 | qupv3_se18_i2c, qupv3_se18_spi |
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| QUPV3_WRAP2_S2 | QUP2 | 19 | 0x00C88000 | 0x00004000 | 584 | qupv3_se19_i2c, qupv3_se19_spi |
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| QUPV3_WRAP2_S3 | QUP2 | 13 | 0x00C8C000 | 0x00004000 | 585 | qupv3_se13_4uart, qupv3_se13_i2c, qupv3_se13_spi |
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| QUPV3_WRAP2_S4 | QUP2 | 14 | 0x00C90000 | 0x00004000 | 586 | qupv3_se14_i2c, qupv3_se14_spi |
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| QUPV3_WRAP2_S5 | QUP2 | 15 | 0x00C94000 | 0x00004000 | 587 | qupv3_se15_i2c, qupv3_se15_spi |
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---
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QUPv3 SSC:
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| Si | QUP | SE | Address | Length | IRQ | Android DT Names |
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|----------------|------|----|------------|------------|-----|--------------------------------|
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| QUPV3_SE0 | QUP3 | 20 | 0x02680000 | 0x00004000 | 442 | qupv3_se20_i2c |
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| QUPV3_SE1 | QUP3 | 21 | 0x02684000 | 0x00004000 | 443 | qupv3_se21_i2c, qupv3_se21_spi |
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| QUPV3_SE2 | QUP3 | 22 | 0x02688000 | 0x00004000 | 444 | qupv3_se22_i2c, qupv3_se22_spi |
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| QUPV3_SE3 | QUP3 | 23 | 0x0268C000 | 0x00004000 | 445 | qupv3_se23_i2c |
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## Misc (MTP8150)
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Available GPIIs:
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| QUP | GPII | Clients |
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|------|------|-------------------|
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| QUP0 | 0 | ADSP |
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| QUP0 | 1 | HLOS / HLOS (GSI) |
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| QUP0 | 2 | ADSP |
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| QUP0 | 3 | HLOS / HLOS (GSI) |
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| QUP0 | 4 | HLOS / HLOS (GSI) |
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| QUP0 | 5 | HLOS / HLOS (GSI) |
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| QUP0 | 6 | HLOS / HLOS (GSI) |
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| QUP0 | 7 | HLOS / HLOS (GSI) |
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| QUP0 | 8 | TZ |
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| QUP0 | 9 | TZ |
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| QUP0 | 10 | ADSP |
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| QUP0 | 11 | ADSP |
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| QUP0 | 12 | MPSS |
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---
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| QUP | GPII | Clients |
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|------|------|-------------------|
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| QUP1 | 0 | ADSP |
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| QUP1 | 1 | HLOS / HLOS (GSI) |
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| QUP1 | 2 | ADSP |
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| QUP1 | 3 | HLOS / HLOS (GSI) |
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| QUP1 | 4 | HLOS / HLOS (GSI) |
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| QUP1 | 5 | HLOS / HLOS (GSI) |
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| QUP1 | 6 | HLOS / HLOS (GSI) |
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| QUP1 | 7 | HLOS / HLOS (GSI) |
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| QUP1 | 8 | TZ |
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| QUP1 | 9 | TZ |
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| QUP1 | 10 | ADSP |
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| QUP1 | 11 | ADSP |
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| QUP1 | 12 | MPSS |
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---
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| QUP | GPII | Clients |
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|------|------|-------------------|
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| QUP2 | 0 | ADSP |
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| QUP2 | 1 | HLOS / HLOS (GSI) |
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| QUP2 | 2 | ADSP |
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| QUP2 | 3 | HLOS / HLOS (GSI) |
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| QUP2 | 4 | HLOS / HLOS (GSI) |
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| QUP2 | 5 | HLOS / HLOS (GSI) |
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| QUP2 | 6 | HLOS / HLOS (GSI) |
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| QUP2 | 7 | HLOS / HLOS (GSI) |
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| QUP2 | 8 | TZ |
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| QUP2 | 9 | TZ |
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| QUP2 | 10 | ADSP |
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| QUP2 | 11 | ADSP |
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| QUP2 | 12 | MPSS |
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Bus Security:
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| QUP | SE | Bus | Operation Mode | Owner | Can Operate in FIFO? | Load GPI FW? | TZ Exclusive Modification? | Notes |
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|------|----|---------------|----------------|-------|----------------------|--------------|----------------------------|-----------------------------|
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| QUP0 | 0 | SPI | GSI | TZ | False | True | True | NFC eSE |
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| QUP0 | 1 | I2C | FIFO | HLOS | True | True | False | SS Sub-PMIC |
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| QUP0 | 2 | SPI | GSI | TZ | False | True | True | Fingerprint |
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| QUP0 | 3 | SPI | GSI | HLOS | True | True | False | WCD936x |
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| QUP0 | 4 | I2C | FIFO | HLOS | True | True | False | Haptics (sensors hub) |
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| QUP0 | 6 | UART (2 wire) | FIFO | HLOS | True | True | False | 5G HS-UART |
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| QUP0 | 7 | I2C | FIFO | HLOS | True | True | False | SS PMIC |
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---
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| QUP | SE | Bus | Operation Mode | Owner | Can Operate in FIFO? | Load GPI FW? | TZ Exclusive Modification? | Notes |
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|------|----|---------------|----------------|-------|----------------------|--------------|----------------------------|-----------------------------|
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| QUP1 | 0 | SPI | GSI | HLOS | True | True | False | SS Camera |
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| QUP1 | 1 | I2C | GSI | HLOS | False | True | False | NFC / Forcetouch |
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| QUP1 | 3 | SPI | GSI | HLOS | True | True | False | SS Camera |
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| QUP1 | 4 | UART (2 wire) | FIFO | HLOS | True | False | False | Debug |
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| QUP1 | 5 | UART (2 wire) | FIFO | HLOS | True | True | False | Napier WiFi |
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---
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| QUP | SE | Bus | Operation Mode | Owner | Can Operate in FIFO? | Load GPI FW? | TZ Exclusive Modification? | Notes |
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|------|----|---------------|----------------|-------|----------------------|--------------|----------------------------|-----------------------------|
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| QUP2 | 0 | I2C | FIFO | HLOS | True | True | False | SS WPC |
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| QUP2 | 2 | I2C | FIFO | HLOS | True | True | False | legacy touch |
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| QUP2 | 3 | UART (4 wire) | FIFO | HLOS | True | True | False | BT HCI |
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## GPI Index (GPII) Assignments for MTP8150
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The Qualcomm Technologies Incorporated Mobile Testing Platform for SM8150 (MTP8150) makes use of the following Buses:

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