Welcome to the Half-Subtractor Design project! 🎉 This repository showcases the implementation of a half-subtractor using Verilog, focusing on gate-level modeling and functional verification. A perfect resource for beginners diving into digital design! 💻✨
| File Name | Description |
|---|---|
| hs.v | Verilog module implementing the half-subtractor with gate-level modeling. |
| hs_tb.v | Testbench for hs.v to validate difference and borrow. |
| hs.vcd | Value Change Dump file generated after simulation for waveform analysis. |
| hs_tb.vvp | Compiled simulation file created by Icarus Verilog. |
LICENSE |
MIT License details. |
The half_subtractor.v file implements the half-subtractor logic:
- Difference (D): Outputs the XOR of inputs A and B.
- Borrow (B): Outputs the NOT of A AND B.
| A | B | Difference (D) | Borrow (B) |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 1 | 1 | 1 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 0 |
The half_subtractor_tb.v file verifies the functionality of the half-subtractor with various test cases. Outputs are logged in the terminal and exported to a .vcd file for waveform analysis.
- Beginner-friendly gate-level design.
- Detailed testbench for thorough validation.
- Clear and modular Verilog code.
For a step-by-step guide on setting up simulations using Icarus Verilog and GTKWave, check out my Logic Gates Simulation Repository. It provides everything you need to compile, simulate, and visualize Verilog designs.
Contributions are highly encouraged to make this project even better! Fork, clone, and share your improvements. 🚀
📜 This project is licensed under the MIT License. See the LICENSE file for details.