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USA-RedDragonUSA-RedDragon
committed
Fix lint issues
1 parent 4c04751 commit 28e7f28

21 files changed

+290
-286
lines changed

‎cmd/go-gba.go

+26-35
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,6 @@ import (
1111
"github.com/USA-RedDragon/go-gba/internal/config"
1212
"github.com/USA-RedDragon/go-gba/internal/emulator"
1313
"github.com/USA-RedDragon/go-gba/internal/emulator/cpu"
14-
1514
"github.com/hajimehoshi/ebiten/v2"
1615
"github.com/spf13/cobra"
1716
)
@@ -72,10 +71,9 @@ func runComparer(cmd *cobra.Command) error {
7271
// mgba PC will be 2 bytes ahead of ours
7372
if mgba.GetRegister(i)-2 == c.ReadRegister(uint8(i)) {
7473
continue
75-
} else {
76-
fmt.Printf("Register %d: %08x != %08x\n", i, mgba.GetRegister(i), c.ReadRegister(uint8(i)))
77-
return nil
7874
}
75+
fmt.Printf("Register %d: %08x != %08x\n", i, mgba.GetRegister(i), c.ReadRegister(uint8(i)))
76+
return nil
7977
}
8078
fmt.Printf("Register %d: %08x != %08x\n", i, mgba.GetRegister(i), c.ReadRegister(uint8(i)))
8179
return nil
@@ -87,12 +85,10 @@ func runComparer(cmd *cobra.Command) error {
8785
return err
8886
}
8987

90-
mgba.Wait()
91-
92-
return nil
88+
return mgba.Wait()
9389
}
9490

95-
func run(cmd *cobra.Command, args []string) error {
91+
func run(cmd *cobra.Command, _ []string) error {
9692
fmt.Printf("go-gba %s-%s\n", cmd.Annotations["version"], cmd.Annotations["commit"])
9793
diff, err := cmd.Flags().GetBool("diff")
9894
if err != nil {
@@ -126,35 +122,30 @@ func run(cmd *cobra.Command, args []string) error {
126122
c := cpu.NewARM7TDMI(config.GetConfig(cmd))
127123
c.Run()
128124
return nil
129-
} else {
130-
config := config.GetConfig(cmd)
131-
132-
emu := emulator.New(config)
133-
go func() {
134-
ch := make(chan os.Signal, 1)
135-
signal.Notify(ch, os.Interrupt)
136-
for range ch {
137-
fmt.Println("Exiting")
138-
emu.Stop()
139-
}
140-
}()
141-
142-
ebiten.SetWindowSize(int(config.Scale*240), int(config.Scale*160))
143-
ebiten.SetWindowResizingMode(ebiten.WindowResizingModeEnabled)
144-
ebiten.SetFullscreen(config.Fullscreen)
145-
ebiten.SetScreenClearedEveryFrame(true)
146-
147-
if config.ROMPath != "" {
148-
name := strings.TrimSuffix(filepath.Base(config.ROMPath), filepath.Ext(config.ROMPath))
149-
ebiten.SetWindowTitle(name + " | go-gba")
150-
} else {
151-
ebiten.SetWindowTitle("go-gba")
125+
}
126+
config := config.GetConfig(cmd)
127+
128+
emu := emulator.New(config)
129+
go func() {
130+
ch := make(chan os.Signal, 1)
131+
signal.Notify(ch, os.Interrupt)
132+
for range ch {
133+
fmt.Println("Exiting")
134+
emu.Stop()
152135
}
136+
}()
153137

154-
if err := ebiten.RunGame(emu); err != nil {
155-
return err
156-
}
138+
ebiten.SetWindowSize(int(config.Scale*240), int(config.Scale*160))
139+
ebiten.SetWindowResizingMode(ebiten.WindowResizingModeEnabled)
140+
ebiten.SetFullscreen(config.Fullscreen)
141+
ebiten.SetScreenClearedEveryFrame(true)
142+
143+
if config.ROMPath != "" {
144+
name := strings.TrimSuffix(filepath.Base(config.ROMPath), filepath.Ext(config.ROMPath))
145+
ebiten.SetWindowTitle(name + " | go-gba")
146+
} else {
147+
ebiten.SetWindowTitle("go-gba")
157148
}
158149

159-
return nil
150+
return ebiten.RunGame(emu)
160151
}

‎internal/config/config.go

+4-2
Original file line numberDiff line numberDiff line change
@@ -82,10 +82,12 @@ func GetConfig(cmd *cobra.Command) *Config {
8282
currentConfig.Interactive = interactive
8383
if interactive {
8484
currentConfig.Debug = true
85-
cmd.Flags().Set("cpu-only", "true")
85+
err := cmd.Flags().Set("cpu-only", "true")
86+
if err != nil {
87+
fmt.Println("Error setting cpu-only flag")
88+
}
8689
}
8790
}
88-
8991
}
9092

9193
fmt.Println(currentConfig.ToString())

‎internal/emulator/cpu/cpu.go

+84-82
Original file line numberDiff line numberDiff line change
@@ -12,6 +12,7 @@ import (
1212
"github.com/USA-RedDragon/go-gba/internal/emulator/ppu"
1313
)
1414

15+
//nolint:golint,revive
1516
const (
1617
// BIOSROMSize is 16KB
1718
BIOSROMSize = 16 * 1024
@@ -29,6 +30,7 @@ const (
2930
CPSR_REG = 16
3031
)
3132

33+
//nolint:golint,revive
3234
type ARM7TDMI struct {
3335
// Registers R0-R16
3436
r [17]uint32
@@ -129,7 +131,7 @@ func (c *ARM7TDMI) DebugRegisters() string {
129131
ret += fmt.Sprintf(" R0: 0x%08X\t R1: 0x%08X\t R2: 0x%08X\t R3: 0x%08X\n", c.ReadRegister(0), c.ReadRegister(1), c.ReadRegister(2), c.ReadRegister(3))
130132
ret += fmt.Sprintf(" R4: 0x%08X\t R5: 0x%08X\t R6: 0x%08X\t R7: 0x%08X\n", c.ReadRegister(4), c.ReadRegister(5), c.ReadRegister(6), c.ReadRegister(7))
131133
if c.GetThumbMode() {
132-
ret += fmt.Sprintf(" R8: 0x%08X\t R9: 0x%08X\tR10: 0x%08X\t R11: 0x%08X\n", c.ReadHighRegister(8-8), c.ReadHighRegister(9-8), c.ReadHighRegister(10-8), c.ReadHighRegister(11-8))
134+
ret += fmt.Sprintf(" R8: 0x%08X\t R9: 0x%08X\tR10: 0x%08X\t R11: 0x%08X\n", c.ReadHighRegister(0), c.ReadHighRegister(9-8), c.ReadHighRegister(10-8), c.ReadHighRegister(11-8))
133135
ret += fmt.Sprintf("R12: 0x%08X\t SP: 0x%08X\t LR: 0x%08X\t PC: 0x%08X\n", c.ReadHighRegister(12-8), c.ReadHighRegister(13-8), c.ReadHighRegister(14-8), c.ReadHighRegister(15-8))
134136
} else {
135137
ret += fmt.Sprintf(" R8: 0x%08X\t R9: 0x%08X\tR10: 0x%08X\t R11: 0x%08X\n", c.ReadRegister(8), c.ReadRegister(9), c.ReadRegister(10), c.ReadRegister(11))
@@ -405,119 +407,122 @@ func (c *ARM7TDMI) WriteHighRegister(reg uint8, value uint32) {
405407
default:
406408
panic("Unknown CPU mode")
407409
}
408-
409410
}
410411

412+
//nolint:golint,gocyclo
411413
func (c *ARM7TDMI) ReadRegister(reg uint8) uint32 {
412414
if c.GetThumbMode() {
413415
if reg > 7 && reg != PC_REG && reg != LR_REG && reg != SP_REG && reg != CPSR_REG {
414416
panic(fmt.Sprintf("Invalid register number %d", reg))
415417
}
416-
if reg == PC_REG {
418+
switch reg {
419+
case PC_REG:
417420
return c.ReadPC()
418-
} else if reg == LR_REG {
421+
case LR_REG:
419422
return c.ReadLR()
420-
} else if reg == SP_REG {
423+
case SP_REG:
421424
return c.ReadSP()
422-
} else if reg == CPSR_REG {
425+
case CPSR_REG:
423426
return c.ReadCPSR()
424427
}
425428
return c.r[reg]
426-
} else {
427-
if reg > 16 {
428-
panic(fmt.Sprintf("Invalid register number %d", reg))
429+
}
430+
if reg > 16 {
431+
panic(fmt.Sprintf("Invalid register number %d", reg))
432+
}
433+
switch cpuMode(c.r[CPSR_REG] & 0x1F) {
434+
case systemMode:
435+
return c.r[reg]
436+
case userMode:
437+
return c.r[reg]
438+
case fiqMode:
439+
switch reg {
440+
case 8:
441+
return c.r8_fiq
442+
case 9:
443+
return c.r9_fiq
444+
case 10:
445+
return c.r10_fiq
446+
case 11:
447+
return c.r11_fiq
448+
case 12:
449+
return c.r12_fiq
450+
case 13:
451+
return c.sp_fiq
452+
case 14:
453+
return c.lr_fiq
454+
default:
455+
return c.r[reg]
456+
}
457+
case irqMode:
458+
switch reg {
459+
case 13:
460+
return c.sp_irq
461+
case 14:
462+
return c.lr_irq
463+
default:
464+
return c.r[reg]
429465
}
430-
switch cpuMode(c.r[CPSR_REG] & 0x1F) {
431-
case systemMode:
466+
case supervisorMode:
467+
switch reg {
468+
case 13:
469+
return c.sp_svc
470+
case 14:
471+
return c.lr_svc
472+
default:
432473
return c.r[reg]
433-
case userMode:
474+
}
475+
case abortMode:
476+
switch reg {
477+
case 13:
478+
return c.sp_abt
479+
case 14:
480+
return c.lr_abt
481+
default:
434482
return c.r[reg]
435-
case fiqMode:
436-
switch reg {
437-
case 8:
438-
return c.r8_fiq
439-
case 9:
440-
return c.r9_fiq
441-
case 10:
442-
return c.r10_fiq
443-
case 11:
444-
return c.r11_fiq
445-
case 12:
446-
return c.r12_fiq
447-
case 13:
448-
return c.sp_fiq
449-
case 14:
450-
return c.lr_fiq
451-
default:
452-
return c.r[reg]
453-
}
454-
case irqMode:
455-
switch reg {
456-
case 13:
457-
return c.sp_irq
458-
case 14:
459-
return c.lr_irq
460-
default:
461-
return c.r[reg]
462-
}
463-
case supervisorMode:
464-
switch reg {
465-
case 13:
466-
return c.sp_svc
467-
case 14:
468-
return c.lr_svc
469-
default:
470-
return c.r[reg]
471-
}
472-
case abortMode:
473-
switch reg {
474-
case 13:
475-
return c.sp_abt
476-
case 14:
477-
return c.lr_abt
478-
default:
479-
return c.r[reg]
480-
}
481-
case undefinedMode:
482-
switch reg {
483-
case 13:
484-
return c.sp_und
485-
case 14:
486-
return c.lr_und
487-
default:
488-
return c.r[reg]
489-
}
483+
}
484+
case undefinedMode:
485+
switch reg {
486+
case 13:
487+
return c.sp_und
488+
case 14:
489+
return c.lr_und
490490
default:
491-
panic("Unknown CPU mode")
491+
return c.r[reg]
492492
}
493+
default:
494+
panic("Unknown CPU mode")
493495
}
494496
}
495497

498+
//nolint:golint,gocyclo
496499
func (c *ARM7TDMI) WriteRegister(reg uint8, value uint32) {
497500
if c.GetThumbMode() {
498501
if reg > 7 && reg != PC_REG && reg != LR_REG && reg != SP_REG && reg != CPSR_REG {
499502
panic(fmt.Sprintf("Invalid register number %d", reg))
500503
}
501-
if reg == PC_REG {
504+
switch reg {
505+
case PC_REG:
502506
c.WritePC(value)
503-
} else if reg == LR_REG {
507+
case LR_REG:
504508
c.WriteLR(value)
505-
} else if reg == SP_REG {
509+
case SP_REG:
506510
c.WriteSP(value)
507-
} else if reg == CPSR_REG {
511+
case CPSR_REG:
508512
c.WriteCPSR(value)
509-
} else {
513+
default:
510514
c.r[reg] = value
511515
}
512516
} else {
513517
if reg > 16 {
514518
panic(fmt.Sprintf("Invalid register number %d", reg))
515519
}
516-
if reg == PC_REG {
520+
switch reg {
521+
case PC_REG:
517522
c.WritePC(value)
518-
} else if reg == LR_REG {
523+
case LR_REG:
519524
c.WriteLR(value)
520-
} else {
525+
default:
521526
switch cpuMode(c.r[CPSR_REG] & 0x1F) {
522527
case systemMode:
523528
c.r[reg] = value
@@ -786,6 +791,7 @@ func (c *ARM7TDMI) fetchThumb() uint16 {
786791
return instruction
787792
}
788793

794+
//nolint:golint,gocyclo
789795
func (c *ARM7TDMI) stepARM() {
790796
// FETCH
791797
instruction := c.fetchARM()
@@ -796,7 +802,7 @@ func (c *ARM7TDMI) stepARM() {
796802
}
797803

798804
// DECODE
799-
var condition uint32 = instruction >> 28
805+
var condition = instruction >> 28
800806
conditionFailed := false
801807
// c.r[CSPR_REG] has condition flags N Z C V at bits 31-28
802808
// c.r[CSPR_REG] has control bits I F T at bits 7-5
@@ -1051,11 +1057,7 @@ func (c *ARM7TDMI) SetThumbMode(value bool) {
10511057
}
10521058

10531059
func (c *ARM7TDMI) GetThumbMode() bool {
1054-
if c.r[CPSR_REG]&(1<<5)>>5 == 0 {
1055-
return false
1056-
} else {
1057-
return true
1058-
}
1060+
return c.r[CPSR_REG]&(1<<5)>>5 != 0
10591061
}
10601062

10611063
// InteractiveRun runs the CPU one instruction at a time, waiting for user input

‎internal/emulator/cpu/isa/arm/alu.go

+1-1
Original file line numberDiff line numberDiff line change
@@ -42,7 +42,7 @@ func ALUOp2(inst uint32, cpu interfaces.CPU) uint32 {
4242

4343
// immediate(op rd, imm)
4444
op2 := inst & 0b1111_1111
45-
is := uint32((inst>>8)&0b1111) * 2
45+
is := ((inst >> 8) & 0b1111) * 2
4646
carryMut := inst&(1<<20)>>20 == 1
4747
fmt.Println("ALUOp2 immediate")
4848
op2 = ROR(op2, is, carryMut, false, cpu)

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