chore(dispatch): remove useless code and files (#4288)

Author: xiaofeibao-xjtu

scripts/top-down/configs.py

@@ -28,10 +28,6 @@
     'IntFlStall': 'MergeFreelistStall',
     'FpFlStall': 'MergeFreelistStall',
 
-    'IntDqStall': 'MergeCoreDQStall',
-    'FpDqStall': 'MergeCoreDQStall',
-    'LsDqStall': 'MergeMemDQStall',
-
     'LoadTLBStall': 'MergeLoad',
     'LoadL1Stall': 'MergeLoad',
     'LoadL2Stall': 'MergeLoad',
@@ -82,10 +78,6 @@
     'IntFlStall': 'MergeFreelistStall',
     'FpFlStall': 'MergeFreelistStall',
 
-    'IntDqStall': 'MergeDispatchQueueStall',
-    'FpDqStall': 'MergeDispatchQueueStall',
-    'LsDqStall': 'MergeDispatchQueueStall',
-
     'LoadTLBStall': 'DTlbStall',
     'LoadL1Stall': 'LoadL1Bound',
     'LoadL2Stall': 'LoadL2Bound',
@@ -142,10 +134,6 @@
     'IntFlStall': fr'{XS_CORE_PREFIX}.backend.ctrlBlock\.dispatch: IntFlStall,\s+(\d+)',
     'FpFlStall': fr'{XS_CORE_PREFIX}.backend.ctrlBlock\.dispatch: FpFlStall,\s+(\d+)',
 
-    'IntDqStall': fr'{XS_CORE_PREFIX}.backend.ctrlBlock\.dispatch: IntDqStall,\s+(\d+)',
-    'FpDqStall': fr'{XS_CORE_PREFIX}.backend.ctrlBlock\.dispatch: FpDqStall,\s+(\d+)',
-    'LsDqStall': fr'{XS_CORE_PREFIX}.backend.ctrlBlock\.dispatch: LsDqStall,\s+(\d+)',
-
     'LoadTLBStall': fr'{XS_CORE_PREFIX}.backend.ctrlBlock\.dispatch: LoadTLBStall,\s+(\d+)',
     'LoadL1Stall': fr'{XS_CORE_PREFIX}.backend.ctrlBlock\.dispatch: LoadL1Stall,\s+(\d+)',
     'LoadL2Stall': fr'{XS_CORE_PREFIX}.backend.ctrlBlock\.dispatch: LoadL2Stall,\s+(\d+)',

src/main/scala/top/Configs.scala

@@ -29,7 +29,6 @@ import xiangshan.frontend.icache.ICacheParameters
 import freechips.rocketchip.devices.debug._
 import openLLC.OpenLLCParam
 import freechips.rocketchip.diplomacy._
-import xiangshan.backend.dispatch.DispatchParameters
 import xiangshan.backend.regfile.{IntPregParams, VfPregParams}
 import xiangshan.cache.DCacheParameters
 import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters}
@@ -96,15 +95,6 @@ class MinimalConfig(n: Int = 1) extends Config(
         StoreBufferThreshold = 3,
         IssueQueueSize = 10,
         IssueQueueCompEntrySize = 4,
-        dpParams = DispatchParameters(
-          IntDqSize = 12,
-          FpDqSize = 12,
-          LsDqSize = 12,
-          IntDqDeqWidth = 8,
-          FpDqDeqWidth = 6,
-          VecDqDeqWidth = 6,
-          LsDqDeqWidth = 6
-        ),
         intPreg = IntPregParams(
           numEntries = 64,
           numRead = None,

src/main/scala/xiangshan/Parameters.scala

@@ -23,7 +23,6 @@ import huancun._
 import system.SoCParamsKey
 import xiangshan.backend.datapath.RdConfig._
 import xiangshan.backend.datapath.WbConfig._
-import xiangshan.backend.dispatch.DispatchParameters
 import xiangshan.backend.exu.ExeUnitParams
 import xiangshan.backend.fu.FuConfig._
 import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler, FpScheduler}
@@ -179,15 +178,6 @@ case class XSCoreParameters
   VTypeBufferSize: Int = 64, // used to reorder vtype
   IssueQueueSize: Int = 24,
   IssueQueueCompEntrySize: Int = 16,
-  dpParams: DispatchParameters = DispatchParameters(
-    IntDqSize = 16,
-    FpDqSize = 16,
-    LsDqSize = 18,
-    IntDqDeqWidth = 8,
-    FpDqDeqWidth = 6,
-    VecDqDeqWidth = 6,
-    LsDqDeqWidth = 6,
-  ),
   intPreg: PregParams = IntPregParams(
     numEntries = 224,
     numRead = None,
@@ -421,7 +411,6 @@ case class XSCoreParameters
       numDeqOutside = 0,
       schdType = schdType,
       rfDataWidth = intPreg.dataCfg.dataWidth,
-      numUopIn = dpParams.IntDqDeqWidth,
     )
   }
 
@@ -444,7 +433,6 @@ case class XSCoreParameters
       numDeqOutside = 0,
       schdType = schdType,
       rfDataWidth = fpPreg.dataCfg.dataWidth,
-      numUopIn = dpParams.FpDqDeqWidth,
     )
   }
 
@@ -467,7 +455,6 @@ case class XSCoreParameters
       numDeqOutside = 0,
       schdType = schdType,
       rfDataWidth = vfPreg.dataCfg.dataWidth,
-      numUopIn = dpParams.VecDqDeqWidth,
     )
   }
 
@@ -508,7 +495,6 @@ case class XSCoreParameters
       numDeqOutside = 0,
       schdType = schdType,
       rfDataWidth = rfDataWidth,
-      numUopIn = dpParams.LsDqDeqWidth,
     )
   }
 
@@ -771,7 +757,7 @@ trait HasXSParameter {
   def maxElemPerVreg: Int = coreParams.maxElemPerVreg
 
   def IntRefCounterWidth = log2Ceil(RobSize)
-  def LSQEnqWidth = coreParams.dpParams.LsDqDeqWidth
+  def LSQEnqWidth = RenameWidth
   def LSQLdEnqWidth = LSQEnqWidth min backendParams.numLoadDp
   def LSQStEnqWidth = LSQEnqWidth min backendParams.numStoreDp
   def VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize
@@ -786,7 +772,6 @@ trait HasXSParameter {
   def StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks
   def StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask
   def VlsQueueSize = coreParams.VlsQueueSize
-  def dpParams = coreParams.dpParams
 
   def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max
   def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max

src/main/scala/xiangshan/backend/BackendParams.scala

@@ -113,7 +113,6 @@ case class BackendParams(
   def CsrCnt = allSchdParams.map(_.CsrCnt).sum
   def IqCnt = allSchdParams.map(_.issueBlockParams.length).sum
 
-  def numPcReadPort = allSchdParams.map(_.numPcReadPort).sum
   def numPcMemReadPort = allExuParams.filter(_.needPc).size
   def numTargetReadPort = allRealExuParams.count(x => x.needTarget)
 

src/main/scala/xiangshan/backend/CtrlBlock.scala

@@ -28,7 +28,7 @@ import xiangshan.backend.Bundles.{DecodedInst, DynInst, ExceptionInfo, ExuOutput
 import xiangshan.backend.ctrlblock.{DebugLSIO, DebugLsInfoBundle, LsTopdownInfo, MemCtrl, RedirectGenerator}
 import xiangshan.backend.datapath.DataConfig.{FpData, IntData, V0Data, VAddrData, VecData, VlData}
 import xiangshan.backend.decode.{DecodeStage, FusionDecoder}
-import xiangshan.backend.dispatch.{CoreDispatchTopDownIO, Dispatch, DispatchQueue}
+import xiangshan.backend.dispatch.{CoreDispatchTopDownIO}
 import xiangshan.backend.dispatch.NewDispatch
 import xiangshan.backend.fu.PFEvent
 import xiangshan.backend.fu.vector.Bundles.{VType, Vl}
@@ -80,12 +80,10 @@ class CtrlBlockImp(
     "trace"     -> TraceGroupNum
   ))
 
-  private val numPcMemReadForExu = params.numPcReadPort
   private val numPcMemRead = pcMemRdIndexes.maxIdx
 
   // now pcMem read for exu is moved to PcTargetMem (OG0)
   println(s"pcMem read num: $numPcMemRead")
-  println(s"pcMem read num for exu: $numPcMemReadForExu")
 
   val io = IO(new CtrlBlockIO())