opae: fix user clock configuration sequence numbers #3156
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The CSR interface for changing the user clock frequency relies on sequence numbers to detect the next command. In normal operation, a command stream ends by forcing the hardware sequence counter to zero. If the command stream is interrupted, the sequence number may be left non-zero. Update the command stream to start counting from the current sequence number in hardware. Signed-off-by: Michael Adler <michael.adler@altera.com>
pcolberg
approved these changes
Jan 29, 2025
Pull Request Test Coverage Report for Build 13041424558Details
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The CSR interface for changing the user clock frequency relies on sequence numbers to detect the next command. In normal operation, a command stream ends by forcing the hardware sequence counter to zero. If the command stream is interrupted, the sequence number may be left non-zero. Update the command stream to start counting from the current sequence number in hardware.
Tests run:
Forced non-zero starting seq on HW, confirmed that commands were detected with Signal Tap.