diff --git a/libraries/CMakeLists.txt b/libraries/CMakeLists.txt index f3c5ba25fb26..13c94a94dce3 100644 --- a/libraries/CMakeLists.txt +++ b/libraries/CMakeLists.txt @@ -75,4 +75,5 @@ opae_add_subdirectory(libboard/board_d5005) opae_add_subdirectory(libboard/board_n6000) opae_add_subdirectory(libboard/board_n5010) opae_add_subdirectory(libboard/board_c6100) +opae_add_subdirectory(libboard/board_jtag_pci_dk) opae_add_subdirectory(libboard/board_cmc) diff --git a/libraries/libboard/board_common/CMakeLists.txt b/libraries/libboard/board_common/CMakeLists.txt index dd6cefe45a81..961c15d16119 100644 --- a/libraries/libboard/board_common/CMakeLists.txt +++ b/libraries/libboard/board_common/CMakeLists.txt @@ -28,5 +28,5 @@ opae_add_static_library(TARGET board_common SOURCE board_common.c ${opae-test_ROOT}/framework/mock/opae_std.c - LIBS opae-c + LIBS opae-c opaeuio ) diff --git a/libraries/libboard/board_common/board_common.c b/libraries/libboard/board_common/board_common.c index 34e151a43870..efc67d557c5f 100644 --- a/libraries/libboard/board_common/board_common.c +++ b/libraries/libboard/board_common/board_common.c @@ -42,6 +42,7 @@ #include #include #include +#include #include #include "board_common.h" @@ -70,6 +71,175 @@ #define DFL_SYSFS_QSFP "*dfl*dev.%ld/qsfp_connected" #define MAX_DEV_FEATURE_COUNT 256 +#define DFH_CSR_ADDR 0x18 +#define DFH_CSR_SIZE 0x20 +#define FPGA_VAR_BUF_LEN 256 + +#define HSSI_FEATURE_ID 0x15 +#define HSSI_100G_PROFILE 27 +#define HSSI_25G_PROFILE 21 +#define HSSI_10_PROFILE 20 + +#define HSSI_FEATURE_LIST 0xC +#define HSSI_PORT_ATTRIBUTE 0x10 +#define HSSI_VERSION 0x8 +#define HSSI_PORT_STATUS 0x818 +#define GET_BIT(var, pos) ((var >> pos) & (1)) + +// hssi version +struct hssi_version { + union { + uint32_t csr; + struct { + uint32_t rsvd : 8; + uint32_t minor : 8; + uint32_t major : 16; + }; + }; +}; + +//Physical Port Enable +/* +[6] - Port 0 Enable +[7] - Port 1 Enable +: +[21] - Port 15 Enable +*/ +#define PORT_ENABLE_COUNT 20 + +// hssi feature list CSR +struct hssi_feature_list { + union { + uint32_t csr; + struct { + uint32_t axi4_support : 1; + uint32_t hssi_num : 5; + uint32_t port_enable : 20; + uint32_t reserved : 6; + }; + }; +}; + +// hssi port attribute CSR +//Interface Attribute Port X Parameters, X =0-15 +//Byte Offset: 0x10 + X * 4 +struct hssi_port_attribute { + union { + uint32_t csr; + struct { + uint32_t profile : 6; + uint32_t ready_latency : 4; + uint32_t data_bus_width : 3; + uint32_t low_speed_mac : 2; + uint32_t dynamic_pr : 1; + uint32_t sub_profile : 5; + uint32_t reserved : 11; + }; + }; +}; + +//HSSI Ethernet Port Status +//Byte Offset: 0x818 +struct hssi_port_status { + union { + uint64_t csr; + struct { + uint64_t txplllocked : 16; + uint64_t txlanestable : 16; + uint64_t rxpcsready : 16; + uint64_t reserved : 16; + }; + }; +}; + + +struct dfh { + union { + uint64_t csr; + struct { + uint64_t id : 12; + uint64_t feature_rev : 4; + uint64_t next : 24; + uint64_t eol : 1; + uint64_t reserved41 : 7; + uint64_t feature_minor_rev : 4; + uint64_t dfh_version : 8; + uint64_t type : 4; + }; + }; +}; + +struct dfh_csr_addr { + union { + uint32_t csr; + struct { + uint64_t rel : 1; + uint64_t addr : 63; + }; + }; +}; + +struct dfh_csr_group { + union { + uint32_t csr; + struct { + uint64_t instance_id : 16; + uint64_t grouping_id : 15; + uint64_t has_params : 1; + uint64_t csr_size : 32; + }; + }; +}; + + + +typedef struct hssi_port_profile { + + uint32_t port_index; + char profile[FPGA_VAR_BUF_LEN]; + +} hssi_port_profile; + +#define HSS_PORT_PROFILE_SIZE 34 + +static hssi_port_profile hssi_port_profiles[] = { + + {.port_index = 0, .profile = "LL100G"}, + {.port_index = 1, .profile = "Ultra100G"}, + {.port_index = 2, .profile = "LL50G"}, + {.port_index = 3, .profile = "LL40G"}, + {.port_index = 4, .profile = "Ultra40G"}, + {.port_index = 5, .profile = "25_50G"}, + {.port_index = 6, .profile = "10_25G"}, + {.port_index = 7, .profile = "MRPHY"}, + {.port_index = 8, .profile = "LL10G"}, + {.port_index = 9, .profile = "TSE PCS"}, + {.port_index = 10, .profile = "TSE MAC"}, + {.port_index = 11, .profile = "Flex-E"}, + {.port_index = 12, .profile = "OTN"}, + {.port_index = 13, .profile = "General PCS-Direct"}, + {.port_index = 14, .profile = "General FEC-Direct"}, + {.port_index = 15, .profile = "General PMA-Direct"}, + {.port_index = 16, .profile = "MII"}, + {.port_index = 17, .profile = "Ethernet PCS-Direct"}, + {.port_index = 18, .profile = "Ethernet FEC-Direct"}, + {.port_index = 19, .profile = "Ethernet PMA-Direct"}, + {.port_index = 20, .profile = "10GbE"}, + {.port_index = 21, .profile = "25GbE"}, + {.port_index = 22, .profile = "40GCAUI-4"}, + {.port_index = 23, .profile = "50GAUI-2"}, + {.port_index = 24, .profile = "50GAUI-1"}, + {.port_index = 25, .profile = "100GAUI-1"}, + {.port_index = 26, .profile = "100GAUI-2"}, + {.port_index = 27, .profile = "100GCAUI-4"}, + {.port_index = 28, .profile = "200GAUI-2"}, + {.port_index = 29, .profile = "200GAUI-4"}, + {.port_index = 30, .profile = "200GAUI-8"}, + {.port_index = 31, .profile = "400GAUI-4"}, + {.port_index = 32, .profile = "400GAUI-8"}, + {.port_index = 33, .profile = "CPRI"} + }; + // Read sysfs fpga_result read_sysfs(fpga_token token, char *sysfs_path, char *sysfs_name, size_t len) @@ -803,4 +973,131 @@ fpga_result qsfp_cable_status(const fpga_token token) } return res; -} \ No newline at end of file +} + +static fpga_result print_hssi_port_status(uint8_t *uio_ptr) +{ + uint32_t i = 0; + uint32_t k = 0; + uint32_t ver_offset = 0; + uint32_t feature_list_offset = 0; + uint32_t port_sts_offset = 0; + uint32_t port_attr_offset = 0; + struct dfh dfh_csr; + struct dfh_csr_addr csr_addr; + struct hssi_port_attribute port_profile; + struct hssi_feature_list feature_list; + struct hssi_version hssi_ver; + struct hssi_port_status port_status; + + if (uio_ptr == NULL) { + OPAE_ERR("Invalid Input parameters"); + return FPGA_INVALID_PARAM; + } + + dfh_csr.csr = *((uint64_t *)(uio_ptr + 0x0)); + // dfhv0 + if ((dfh_csr.feature_rev == 0) || + (dfh_csr.feature_rev == 0x1)) { + ver_offset = HSSI_VERSION; + feature_list_offset = HSSI_FEATURE_LIST; + port_sts_offset = HSSI_PORT_STATUS; + port_attr_offset = HSSI_PORT_ATTRIBUTE; + } else if ((dfh_csr.feature_rev >= 0x2) && (dfh_csr.feature_rev < 0xf)) { // dfhv0.5 + csr_addr.csr = *((uint64_t *)(uio_ptr + DFH_CSR_ADDR)); + ver_offset = csr_addr.addr; + feature_list_offset = csr_addr.addr + 0x4; + port_sts_offset = HSSI_PORT_STATUS; + port_attr_offset = csr_addr.addr + 0x8; + + } else { + printf("DFH feature revision not supported:%x \n", dfh_csr.feature_rev); + return FPGA_NOT_SUPPORTED; + } + + feature_list.csr = *((uint32_t *)(uio_ptr + feature_list_offset)); + hssi_ver.csr = *((uint32_t *)(uio_ptr + ver_offset)); + port_status.csr = *((volatile uint64_t *)(uio_ptr + + port_sts_offset)); + + printf("//****** HSSI information ******//\n"); + printf("%-32s : %d.%d \n", "HSSI version", hssi_ver.major, hssi_ver.minor); + printf("%-32s : %d \n", "Number of ports", feature_list.hssi_num); + + for (i = 0; i < PORT_ENABLE_COUNT; i++) { + + // prints only active/enabled ports + if ((GET_BIT(feature_list.port_enable, i) == 0)) { + continue; + } + + port_profile.csr = *((volatile uint32_t *)(uio_ptr + + port_attr_offset + i * 4)); + + if (port_profile.profile > HSS_PORT_PROFILE_SIZE) { + printf("Port%-28d :%s\n", i, "N/A"); + continue; + } + + for (int j = 0; j < HSS_PORT_PROFILE_SIZE; j++) { + if (hssi_port_profiles[j].port_index == port_profile.profile) { + // lock, tx, rx bits set - link status UP + // lock, tx, rx bits not set - link status DOWN + if ((GET_BIT(port_status.txplllocked, k) == 1) && + (GET_BIT(port_status.txlanestable, k) == 1) && + (GET_BIT(port_status.rxpcsready, k) == 1)) { + printf("Port%-28d :%-12s %s\n", i, + hssi_port_profiles[j].profile, "UP"); + } else { + printf("Port%-28d :%-12s %s\n", i, + hssi_port_profiles[j].profile, "DOWN"); + } + k++; + break; + } + } + } + + return FPGA_OK; +} + +// print phy group information +fpga_result print_common_phy_info(fpga_token token) +{ + fpga_result res = FPGA_OK; + struct opae_uio uio; + char feature_dev[SYSFS_PATH_MAX] = { 0 }; + uint8_t *mmap_ptr = NULL; + + res = qsfp_cable_status(token); + if (res != FPGA_OK) { + OPAE_MSG("Failed to find QSFP cable info"); + } + + res = find_dev_feature(token, HSSI_FEATURE_ID, feature_dev); + if (res != FPGA_OK) { + OPAE_MSG("Failed to find feature HSSI"); + return res; + } + + res = opae_uio_open(&uio, feature_dev); + if (res) { + OPAE_ERR("Failed to open uio"); + return res; + } + + res = opae_uio_region_get(&uio, 0, (uint8_t **)&mmap_ptr, NULL); + if (res) { + OPAE_ERR("Failed to get uio region"); + opae_uio_close(&uio); + return res; + } + + res = print_hssi_port_status(mmap_ptr); + if (res) { + OPAE_ERR("Failed to read hssi port status"); + } + + opae_uio_close(&uio); + return res; +} diff --git a/libraries/libboard/board_common/board_common.h b/libraries/libboard/board_common/board_common.h index 7f1ae1e421ba..d622ff1128fc 100644 --- a/libraries/libboard/board_common/board_common.h +++ b/libraries/libboard/board_common/board_common.h @@ -196,6 +196,14 @@ fpga_result reformat_bom_info( */ fpga_result qsfp_cable_status(const fpga_token token); +/** +* prints common phy information, including qsfp_cable_status +* +* @param[in] token fpga_token object for device (FPGA_DEVICE type) +* @returns FPGA_OK on success. +* FPGA_EXCEPTION if invalid sysfs path +*/ +fpga_result print_common_phy_info(fpga_token token); #ifdef __cplusplus } diff --git a/libraries/libboard/board_jtag_pci_dk/CMakeLists.txt b/libraries/libboard/board_jtag_pci_dk/CMakeLists.txt new file mode 100644 index 000000000000..a4ea56f57a9f --- /dev/null +++ b/libraries/libboard/board_jtag_pci_dk/CMakeLists.txt @@ -0,0 +1,40 @@ +## Copyright(c) 2024, Intel Corporation +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following conditions are met: +## +## * Redistributions of source code must retain the above copyright notice, +## this list of conditions and the following disclaimer. +## * Redistributions in binary form must reproduce the above copyright notice, +## this list of conditions and the following disclaimer in the documentation +## and/or other materials provided with the distribution. +## * Neither the name of Intel Corporation nor the names of its contributors +## may be used to endorse or promote products derived from this software +## without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +## ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +## LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +## CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +## SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +## INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +## ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +## POSSIBILITY OF SUCH DAMAGE. + +opae_add_module_library(TARGET board_jtag_pci_dk + SOURCE board_jtag_pci_dk.c + LIBS + ${CMAKE_THREAD_LIBS_INIT} + opae-c + opaeuio + board_common + COMPONENT opaeboardlib +) + +target_include_directories(board_jtag_pci_dk + PRIVATE + ${OPAE_LIB_SOURCE}/libboard/board_common +) diff --git a/libraries/libboard/board_jtag_pci_dk/board_jtag_pci_dk.c b/libraries/libboard/board_jtag_pci_dk/board_jtag_pci_dk.c new file mode 100644 index 000000000000..6e414adf3e41 --- /dev/null +++ b/libraries/libboard/board_jtag_pci_dk/board_jtag_pci_dk.c @@ -0,0 +1,76 @@ +// Copyright(c) 2024, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +#ifdef HAVE_CONFIG_H +#include +#endif // HAVE_CONFIG_H + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "board_jtag_pci_dk.h" +#include "../board_common/board_common.h" + +#define MAC_BUF_LEN 19 + +// print board information +fpga_result print_board_info(fpga_token __attribute__((unused)) token) +{ + fpga_result resval = FPGA_OK; + + return resval; +} + +// print mac information +fpga_result print_mac_info(fpga_token __attribute__((unused)) token) +{ + fpga_result res = FPGA_OK; + + return res; +} + +// print phy group information +fpga_result print_phy_info(fpga_token token) +{ + return print_common_phy_info(token); +} + +// prints fpga boot page info +fpga_result fpga_boot_info(fpga_token token) +{ + return print_common_boot_info(token); +} diff --git a/libraries/libboard/board_jtag_pci_dk/board_jtag_pci_dk.h b/libraries/libboard/board_jtag_pci_dk/board_jtag_pci_dk.h new file mode 100644 index 000000000000..5c7196d434c7 --- /dev/null +++ b/libraries/libboard/board_jtag_pci_dk/board_jtag_pci_dk.h @@ -0,0 +1,74 @@ +// Copyright(c) 2019-2024, Intel Corporation +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// * Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// * Neither the name of Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +#ifndef __FPGA_BOARD_JTAG_PCI_DK_H__ +#define __FPGA_BOARD_JTAG_PCI_DK_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define FPGA_VAR_BUF_LEN 256 + + +/** +* Prints BMC, MAX10 and NIOS version. +* +* @param[in] token fpga_token object for device (FPGA_DEVICE type) +* @returns FPGA_OK on success. FPGA_NOT_FOUND if MAX10 or NIOS sysfs not found. +* FPGA_INVALID_PARAM if invalid parameters were provided +* +*/ +fpga_result print_board_info(fpga_token token); + +/** +* Prints mac informantion. +* +* @param[in] token fpga_token object for device (FPGA_DEVICE type) +* @returns FPGA_OK on success. FPGA_NOT_FOUND if mac sysfs not found. +* FPGA_INVALID_PARAM if invalid parameters were provide +* +*/ +fpga_result print_mac_info(fpga_token token); + + +/** +* Prints fpga boot page info. +* +* @param[in] token fpga_token object for device (FPGA_DEVICE type) +* @returns FPGA_OK on success. FPGA_NOT_FOUND if invalid boot info. +* FPGA_INVALID_PARAM if invalid parameters were provided +* +*/ +fpga_result fpga_boot_info(fpga_token token); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __FPGA_BOARD_JTAG_PCI_DK_H__ */ diff --git a/libraries/libboard/board_n6000/CMakeLists.txt b/libraries/libboard/board_n6000/CMakeLists.txt index 68e42eef32f2..03d565dd9d00 100644 --- a/libraries/libboard/board_n6000/CMakeLists.txt +++ b/libraries/libboard/board_n6000/CMakeLists.txt @@ -32,7 +32,6 @@ opae_add_module_library(TARGET board_n6000 LIBS ${CMAKE_THREAD_LIBS_INIT} opae-c - opaeuio board_common COMPONENT opaeboardlib ) diff --git a/libraries/libboard/board_n6000/board_n6000.c b/libraries/libboard/board_n6000/board_n6000.c index 5fb463fe8294..14a2c47b06e9 100644 --- a/libraries/libboard/board_n6000/board_n6000.c +++ b/libraries/libboard/board_n6000/board_n6000.c @@ -36,7 +36,6 @@ #include #include #include -#include #include "../board_common/board_common.h" #include "board_event_log.h" #include "board_n6000.h" @@ -68,16 +67,6 @@ #define DFL_SEC_SR_SDM_ROOT DFL_SEC_PMCI_GLOB "sr_sdm_root_entry_hash" -#define HSSI_FEATURE_ID 0x15 -#define HSSI_100G_PROFILE 27 -#define HSSI_25G_PROFILE 21 -#define HSSI_10_PROFILE 20 - -#define HSSI_FEATURE_LIST 0xC -#define HSSI_PORT_ATTRIBUTE 0x10 -#define HSSI_VERSION 0x8 -#define HSSI_PORT_STATUS 0x818 - // boot page info sysfs #define DFL_SYSFS_BOOT_GLOB "*dfl*/**/fpga_boot_image" #define BOOTPAGE_PATTERN "_([0-9a-zA-Z]+)" @@ -87,7 +76,6 @@ #define IMAGE_INFO_STRIDE 4096 #define IMAGE_INFO_SIZE 32 #define IMAGE_INFO_COUNT 3 -#define GET_BIT(var, pos) ((var >> pos) & (1)) // event log #define DFL_SYSFS_EVENT_LOG_GLOB "*dfl*/**/bmc_event_log*/nvmem" @@ -96,163 +84,6 @@ #define DFL_SYSFS_BOM_INFO_GLOB "*dfl*/**/bom_info*/nvmem" #define FPGA_BOM_INFO_BUF_LEN 0x2000 -#define DFH_CSR_ADDR 0x18 -#define DFH_CSR_SIZE 0x20 - -// hssi version -struct hssi_version { - union { - uint32_t csr; - struct { - uint32_t rsvd : 8; - uint32_t minor : 8; - uint32_t major : 16; - }; - }; -}; - -//Physical Port Enable -/* -[6] - Port 0 Enable -[7] - Port 1 Enable -: -[21] - Port 15 Enable -*/ -#define PORT_ENABLE_COUNT 20 - -// hssi feature list CSR -struct hssi_feature_list { - union { - uint32_t csr; - struct { - uint32_t axi4_support : 1; - uint32_t hssi_num : 5; - uint32_t port_enable : 20; - uint32_t reserved : 6; - }; - }; -}; - -// hssi port attribute CSR -//Interface Attribute Port X Parameters, X =0-15 -//Byte Offset: 0x10 + X * 4 -struct hssi_port_attribute { - union { - uint32_t csr; - struct { - uint32_t profile : 6; - uint32_t ready_latency : 4; - uint32_t data_bus_width : 3; - uint32_t low_speed_mac : 2; - uint32_t dynamic_pr : 1; - uint32_t sub_profile : 5; - uint32_t reserved : 11; - }; - }; -}; - -//HSSI Ethernet Port Status -//Byte Offset: 0x818 -struct hssi_port_status { - union { - uint64_t csr; - struct { - uint64_t txplllocked : 16; - uint64_t txlanestable : 16; - uint64_t rxpcsready : 16; - uint64_t reserved : 16; - }; - }; -}; - - -struct dfh { - union { - uint64_t csr; - struct { - uint64_t id : 12; - uint64_t feature_rev : 4; - uint64_t next : 24; - uint64_t eol : 1; - uint64_t reserved41 : 7; - uint64_t feature_minor_rev : 4; - uint64_t dfh_version : 8; - uint64_t type : 4; - }; - }; -}; - -struct dfh_csr_addr { - union { - uint32_t csr; - struct { - uint64_t rel : 1; - uint64_t addr : 63; - }; - }; -}; - -struct dfh_csr_group { - union { - uint32_t csr; - struct { - uint64_t instance_id : 16; - uint64_t grouping_id : 15; - uint64_t has_params : 1; - uint64_t csr_size : 32; - }; - }; -}; - - - -typedef struct hssi_port_profile { - - uint32_t port_index; - char profile[FPGA_VAR_BUF_LEN]; - -} hssi_port_profile; - -#define HSS_PORT_PROFILE_SIZE 34 - -hssi_port_profile hssi_port_profiles[] = { - - {.port_index = 0, .profile = "LL100G"}, - {.port_index = 1, .profile = "Ultra100G"}, - {.port_index = 2, .profile = "LL50G"}, - {.port_index = 3, .profile = "LL40G"}, - {.port_index = 4, .profile = "Ultra40G"}, - {.port_index = 5, .profile = "25_50G"}, - {.port_index = 6, .profile = "10_25G"}, - {.port_index = 7, .profile = "MRPHY"}, - {.port_index = 8, .profile = "LL10G"}, - {.port_index = 9, .profile = "TSE PCS"}, - {.port_index = 10, .profile = "TSE MAC"}, - {.port_index = 11, .profile = "Flex-E"}, - {.port_index = 12, .profile = "OTN"}, - {.port_index = 13, .profile = "General PCS-Direct"}, - {.port_index = 14, .profile = "General FEC-Direct"}, - {.port_index = 15, .profile = "General PMA-Direct"}, - {.port_index = 16, .profile = "MII"}, - {.port_index = 17, .profile = "Ethernet PCS-Direct"}, - {.port_index = 18, .profile = "Ethernet FEC-Direct"}, - {.port_index = 19, .profile = "Ethernet PMA-Direct"}, - {.port_index = 20, .profile = "10GbE"}, - {.port_index = 21, .profile = "25GbE"}, - {.port_index = 22, .profile = "40GCAUI-4"}, - {.port_index = 23, .profile = "50GAUI-2"}, - {.port_index = 24, .profile = "50GAUI-1"}, - {.port_index = 25, .profile = "100GAUI-1"}, - {.port_index = 26, .profile = "100GAUI-2"}, - {.port_index = 27, .profile = "100GCAUI-4"}, - {.port_index = 28, .profile = "200GAUI-2"}, - {.port_index = 29, .profile = "200GAUI-4"}, - {.port_index = 30, .profile = "200GAUI-8"}, - {.port_index = 31, .profile = "400GAUI-4"}, - {.port_index = 32, .profile = "400GAUI-8"}, - {.port_index = 33, .profile = "CPRI"} - }; - // Parse firmware version fpga_result parse_fw_ver(char *buf, char *fw_ver, size_t len) @@ -505,42 +336,7 @@ fpga_result print_board_info(fpga_token token) // print phy group information fpga_result print_phy_info(fpga_token token) { - fpga_result res = FPGA_OK; - struct opae_uio uio; - char feature_dev[SYSFS_PATH_MAX] = { 0 }; - uint8_t *mmap_ptr = NULL; - - res = qsfp_cable_status(token); - if (res != FPGA_OK) { - OPAE_MSG("Failed to find QSFP cable info"); - } - - res = find_dev_feature(token, HSSI_FEATURE_ID, feature_dev); - if (res != FPGA_OK) { - OPAE_MSG("Failed to find feature HSSI"); - return res; - } - - res = opae_uio_open(&uio, feature_dev); - if (res) { - OPAE_ERR("Failed to open uio"); - return res; - } - - res = opae_uio_region_get(&uio, 0, (uint8_t **)&mmap_ptr, NULL); - if (res) { - OPAE_ERR("Failed to get uio region"); - opae_uio_close(&uio); - return res; - } - - res = print_hssi_port_status(mmap_ptr); - if (res) { - OPAE_ERR("Failed to read hssi port status"); - } - - opae_uio_close(&uio); - return res; + return print_common_phy_info(token); } // Sec info @@ -869,88 +665,3 @@ fpga_result fpga_event_log(fpga_token token, uint32_t first, uint32_t last, return FPGA_OK; } -fpga_result print_hssi_port_status(uint8_t *uio_ptr) -{ - uint32_t i = 0; - uint32_t k = 0; - uint32_t ver_offset = 0; - uint32_t feature_list_offset = 0; - uint32_t port_sts_offset = 0; - uint32_t port_attr_offset = 0; - struct dfh dfh_csr; - struct dfh_csr_addr csr_addr; - struct hssi_port_attribute port_profile; - struct hssi_feature_list feature_list; - struct hssi_version hssi_ver; - struct hssi_port_status port_status; - - if (uio_ptr == NULL) { - OPAE_ERR("Invalid Input parameters"); - return FPGA_INVALID_PARAM; - } - - dfh_csr.csr = *((uint64_t *)(uio_ptr + 0x0)); - // dfhv0 - if ((dfh_csr.feature_rev == 0) || - (dfh_csr.feature_rev == 0x1)) { - ver_offset = HSSI_VERSION; - feature_list_offset = HSSI_FEATURE_LIST; - port_sts_offset = HSSI_PORT_STATUS; - port_attr_offset = HSSI_PORT_ATTRIBUTE; - } else if ((dfh_csr.feature_rev >= 0x2) && (dfh_csr.feature_rev < 0xf)) { // dfhv0.5 - csr_addr.csr = *((uint64_t *)(uio_ptr + DFH_CSR_ADDR)); - ver_offset = csr_addr.addr; - feature_list_offset = csr_addr.addr + 0x4; - port_sts_offset = HSSI_PORT_STATUS; - port_attr_offset = csr_addr.addr + 0x8; - - } else { - printf("DFH feature revision not supported:%x \n", dfh_csr.feature_rev); - return FPGA_NOT_SUPPORTED; - } - - feature_list.csr = *((uint32_t *)(uio_ptr + feature_list_offset)); - hssi_ver.csr = *((uint32_t *)(uio_ptr + ver_offset)); - port_status.csr = *((volatile uint64_t *)(uio_ptr - + port_sts_offset)); - - printf("//****** HSSI information ******//\n"); - printf("%-32s : %d.%d \n", "HSSI version", hssi_ver.major, hssi_ver.minor); - printf("%-32s : %d \n", "Number of ports", feature_list.hssi_num); - - for (i = 0; i < PORT_ENABLE_COUNT; i++) { - - // prints only active/enabled ports - if ((GET_BIT(feature_list.port_enable, i) == 0)) { - continue; - } - - port_profile.csr = *((volatile uint32_t *)(uio_ptr + - port_attr_offset + i * 4)); - - if (port_profile.profile > HSS_PORT_PROFILE_SIZE) { - printf("Port%-28d :%s\n", i, "N/A"); - continue; - } - - for (int j = 0; j < HSS_PORT_PROFILE_SIZE; j++) { - if (hssi_port_profiles[j].port_index == port_profile.profile) { - // lock, tx, rx bits set - link status UP - // lock, tx, rx bits not set - link status DOWN - if ((GET_BIT(port_status.txplllocked, k) == 1) && - (GET_BIT(port_status.txlanestable, k) == 1) && - (GET_BIT(port_status.rxpcsready, k) == 1)) { - printf("Port%-28d :%-12s %s\n", i, - hssi_port_profiles[j].profile, "UP"); - } else { - printf("Port%-28d :%-12s %s\n", i, - hssi_port_profiles[j].profile, "DOWN"); - } - k++; - break; - } - } - } - - return FPGA_OK; -} diff --git a/libraries/libopae-c/cfg-file.c b/libraries/libopae-c/cfg-file.c index 9573b855ddee..29a1e4432e38 100644 --- a/libraries/libopae-c/cfg-file.c +++ b/libraries/libopae-c/cfg-file.c @@ -293,6 +293,13 @@ STATIC libopae_config_data default_libopae_config_table[] = { { 0x8086, 0xbccf, 0x8086, 0x0000, "libopae-u.so", "{}", 0 }, // OFS + { 0x8086, 0xbcce, 0x8086, 0x0001, "libxfpga.so", "{}", 0 }, // OFS + { 0x8086, 0xbcce, 0x8086, 0x0001, "libopae-v.so", "{}", 0 }, // OFS + { 0x8086, 0xbccf, 0x8086, 0x0001, "libopae-v.so", "{}", 0 }, // OFS + { 0x8086, 0xbcce, 0x8086, 0x0001, "libopae-u.so", "{}", 0 }, // OFS + { 0x8086, 0xbccf, 0x8086, 0x0001, "libopae-u.so", "{}", 0 }, // OFS + + { 0x8086, 0xbcce, 0x8086, 0x1770, "libxfpga.so", "{}", 0 }, // N6000 { 0x8086, 0xbcce, 0x8086, 0x1770, "libopae-v.so", "{}", 0 }, // N6000 { 0x8086, 0xbccf, 0x8086, 0x1770, "libopae-v.so", "{}", 0 }, // N6000 @@ -438,9 +445,16 @@ STATIC fpgainfo_config_data default_fpgainfo_config_table[] = { { 0x8086, 0xbcce, 0x8086, 0x17d4, 0x12, "libboard_c6100.so", NULL, "Intel IPU Platform F2000X-PL" }, - { 0x8086, 0x0ddb, 0x8086, 0x0, 0x23, "libboard_cmc.so", NULL, + + { 0x8086, 0x0ddb, 0x8086, 0x0, 0x23, "libboard_cmc.so", NULL, "Intel Acceleration Development Platform CMC" }, + { 0x8086, 0xbcce, 0x8086, 0x0001, 0x0, "libboard_jtag_pci_dk.so", NULL, + "Intel Acceleration Development Platform 0001" }, + + { 0x8086, 0xbccf, 0x8086, 0x0001, 0x0, "libboard_jtag_pci_dk.so", NULL, + "Intel Acceleration Development Platform 0001" }, + { 0, 0, 0, 0, -1, NULL, NULL, "" } }; diff --git a/opae.cfg b/opae.cfg index 4d75a49e68d8..b9fc3ecfdc75 100644 --- a/opae.cfg +++ b/opae.cfg @@ -575,6 +575,86 @@ } }, + "0000": { + "enabled": true, + "platform": "Intel Acceleration JTAG PCI Development Kit", + + "devices": [ + { "name": "0000_pf", "id": [ "0x8086", "0xbcce", "0x8086", "0x0001" ] }, + { "name": "0000_vf", "id": [ "0x8086", "0xbccf", "0x8086", "0x0001" ] } + ], + + "opae": { + "plugin": [ + { + "enabled": true, + "module": "libxfpga.so", + "devices": [ "0000_pf" ], + "configuration": {} + }, + { + "enabled": true, + "module": "libopae-v.so", + "devices": [ "0000_pf", "0000_vf" ], + "configuration": {} + }, + { + "enabled": true, + "module": "libopae-u.so", + "devices": [ "0000_pf", "0000_vf" ], + "configuration": {} + } + ], + "fpgainfo": [ + { + "enabled": true, + "module": "libboard_0001.so", + "devices": [ + { "device": "0000_pf", "feature_id": "*" }, + { "device": "0000_vf", "feature_id": "*" } + ] + } + ], + "fpgad": [ + { + "enabled": true, + "module": "libfpgad-vc.so", + "devices": [ "0000_pf" ], + "configuration": { + "cool-down": 30, + "get-aer": [ "setpci -s %s ECAP_AER+0x08.L", + "setpci -s %s ECAP_AER+0x14.L" ], + "disable-aer": [ "setpci -s %s ECAP_AER+0x08.L=0xffffffff", + "setpci -s %s ECAP_AER+0x14.L=0xffffffff" ], + "set-aer": [ "setpci -s %s ECAP_AER+0x08.L=0x%08x", + "setpci -s %s ECAP_AER+0x14.L=0x%08x" ], + "sensor-overrides": [], + "monitor-seu": false + } + } + ], + "rsu": [ + { + "enabled": true, + "devices": [ "0000_pf" ], + "fpga_default_sequences": "common_rsu_sequences" + } + ], + "fpgareg": [ + { + "enabled": true, + "devices": [ "0000_pf", "0000_vf" ] + } + ], + "opae.io": [ + { + "enabled": true, + "devices": [ "0000_pf", "0000_vf" ] + } + ] + } + }, + "c6100": { "enabled": true, "platform": "Intel IPU Platform F2000X-PL", diff --git a/opae.spec.fedora b/opae.spec.fedora index c3228be1ce39..4e4e0be3c119 100644 --- a/opae.spec.fedora +++ b/opae.spec.fedora @@ -222,6 +222,7 @@ done %{_libdir}/opae/libboard_d5005.so %{_libdir}/opae/libboard_n5010.so %{_libdir}/opae/libboard_n6000.so +%{_libdir}/opae/libboard_jtag_pci_dk.so %{_libdir}/opae/libboard_c6100.so %{_libdir}/opae/libboard_cmc.so diff --git a/opae.spec.in b/opae.spec.in index 4d729ab2bb70..e81cdc6475d9 100644 --- a/opae.spec.in +++ b/opae.spec.in @@ -189,6 +189,7 @@ ldconfig @CMAKE_INSTALL_PREFIX@/@OPAE_LIB_INSTALL_DIR@/opae/libboard_n5010.so* @CMAKE_INSTALL_PREFIX@/@OPAE_LIB_INSTALL_DIR@/opae/libboard_a10gx.so* @CMAKE_INSTALL_PREFIX@/@OPAE_LIB_INSTALL_DIR@/opae/libboard_n6000.so* +@CMAKE_INSTALL_PREFIX@/@OPAE_LIB_INSTALL_DIR@/opae/libboard_jtag_pci_dk.so* @CMAKE_INSTALL_PREFIX@/@OPAE_LIB_INSTALL_DIR@/opae/libboard_c6100.so* diff --git a/opae.spec.rhel b/opae.spec.rhel index c7037371c775..82b1a4d1e50d 100644 --- a/opae.spec.rhel +++ b/opae.spec.rhel @@ -185,6 +185,7 @@ done %{_libdir}/opae/libboard_d5005.so %{_libdir}/opae/libboard_n5010.so %{_libdir}/opae/libboard_n6000.so +%{_libdir}/opae/libboard_jtag_pci_dk.so %{_libdir}/opae/libboard_c6100.so %{_libdir}/opae/libboard_cmc.so diff --git a/packaging/opae/deb/opae.install b/packaging/opae/deb/opae.install index 1adc95219722..cd3992df9a14 100644 --- a/packaging/opae/deb/opae.install +++ b/packaging/opae/deb/opae.install @@ -25,6 +25,7 @@ usr/lib/opae/libboard_n3000.so usr/lib/opae/libboard_d5005.so usr/lib/opae/libboard_n5010.so usr/lib/opae/libboard_n6000.so +usr/lib/opae/libboard_jtag_pci_dk.so usr/lib/opae/libboard_c6100.so usr/lib/opae/libboard_cmc.so usr/bin/fpgad diff --git a/tests/board/CMakeLists.txt b/tests/board/CMakeLists.txt index 1133a06a5426..c4094b825a39 100644 --- a/tests/board/CMakeLists.txt +++ b/tests/board/CMakeLists.txt @@ -48,12 +48,14 @@ opae_test_add_static_lib(TARGET board-d5005-static SOURCE ${OPAE_LIB_SOURCE}/libboard/board_d5005/board_d5005.c LIBS opae-c + opaeuio ) opae_test_add_static_lib(TARGET board-n5010-static SOURCE ${OPAE_LIB_SOURCE}/libboard/board_n5010/board_n5010.c LIBS opae-c + opaeuio ) opae_test_add_static_lib(TARGET board-n6000-static diff --git a/tests/fpgainfo/CMakeLists.txt b/tests/fpgainfo/CMakeLists.txt index 4880f010f864..71ff03d76a78 100644 --- a/tests/fpgainfo/CMakeLists.txt +++ b/tests/fpgainfo/CMakeLists.txt @@ -53,10 +53,12 @@ opae_test_add(TARGET test_fpgainfo_c SOURCE test_fpgainfo_c.cpp LIBS fpgainfo-static board-common-static + opaeuio ) opae_test_add(TARGET test_fpgainfo_board_c SOURCE test_board_c.cpp LIBS fpgainfo-static board-common-static + opaeuio )