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Concertando acesso aos perifericos
Concertando resposta a cache quando um periferico e acessado. Concertando shift aritmetico da ALU. Iniciando a criação de testes unitarios.
1 parent adb0361 commit d74b96b

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-663
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‎.github/workflows/alu.yml

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name: ALU Test
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on: [push, pull_request]
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jobs:
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test:
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runs-on: ubuntu-latest
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steps:
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- name: Checkout do código
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uses: actions/checkout@v4
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- name: Instalar Icarus Verilog (iverilog)
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run: sudo apt update && sudo apt install -y iverilog gtkwave
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- name: Criar diretório de build
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run: mkdir -p build
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- name: Compilar o testbench
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run: iverilog -o build/alu_tb -s alu_tb -g2005-sv -Irtl/core testbenchs/alu_tb.sv rtl/core/alu.sv
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- name: Executar o testbench
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run: vvp build/alu_tb
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- name: Salvar VCD como artefato
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uses: actions/upload-artifact@v4
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with:
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name: mdu_waveform
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path: build/alu_tb.vcd

‎.github/workflows/fifo.yml

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name: FIFO Test
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on: [push, pull_request]
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jobs:
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test:
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runs-on: ubuntu-latest
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steps:
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- name: Checkout do código
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uses: actions/checkout@v4
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- name: Instalar Icarus Verilog (iverilog)
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run: sudo apt update && sudo apt install -y iverilog gtkwave
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- name: Criar diretório de build
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run: mkdir -p build
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- name: Compilar o testbench
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run: iverilog -o build/fifo_tb -s fifo_tb -g2005-sv -Irtl/core testbenchs/fifo_tb.sv rtl/peripheral/fifo.sv
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- name: Executar o testbench
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run: vvp build/fifo_tb
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- name: Salvar VCD como artefato
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uses: actions/upload-artifact@v4
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with:
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name: mdu_waveform
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path: build/fifo_tb.vcd

‎.github/workflows/mdu.yml

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name: MDU Test
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on: [push, pull_request]
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jobs:
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test:
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runs-on: ubuntu-latest
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steps:
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- name: Checkout do código
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uses: actions/checkout@v4
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- name: Instalar Icarus Verilog (iverilog)
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run: sudo apt update && sudo apt install -y iverilog gtkwave
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- name: Criar diretório de build
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run: mkdir -p build
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- name: Compilar o testbench
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run: iverilog -o build/mdu_tb -s mdu_tb -g2005-sv -Irtl/core testbenchs/mdu_tb.sv rtl/core/mdu.sv
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- name: Executar o testbench
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run: vvp build/mdu_tb
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- name: Salvar VCD como artefato
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uses: actions/upload-artifact@v4
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with:
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name: mdu_waveform
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path: build/mdu_tb.vcd

‎fpga/colorlight_i9/Makefile

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@@ -17,6 +17,7 @@ buildFolder:
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clean:
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rm -rf build
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rm -rf slpp_all
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load:
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openFPGALoader -b colorlight-i9 ./build/out.bit

‎fpga/nexys4_ddr/main.sv

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@@ -21,7 +21,7 @@ Grande_Risco_5_SOC #(
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.CLOCK_FREQ (50000000),
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.BAUD_RATE (115200),
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.MEMORY_SIZE (16384),
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.MEMORY_FILE ("../../verification_tests/memory/led_test2.hex"),
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.MEMORY_FILE ("../../verification_tests/memory/teste_uart_tx.hex"),
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.GPIO_WIDTH (6),
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.UART_BUFFER_SIZE (32),
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.I_CACHE_SIZE (2048),

‎fpga/nexys4_ddr/reports/clock_utilization.rpt

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Large diffs are not rendered by default.

‎fpga/nexys4_ddr/reports/control_sets.rpt

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Large diffs are not rendered by default.

‎fpga/nexys4_ddr/reports/drc.rpt

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Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
22
---------------------------------------------------------------------------------------------------------------------------------------------
33
| Tool Version : Vivado v.2024.2 (lin64) Build 5239630 Fri Nov 08 22:34:34 MST 2024
4-
| Date : Fri Mar 14 22:23:07 2025
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| Date : Sat Mar 15 01:45:49 2025
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| Host : vader running 64-bit Arch Linux
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| Command : report_drc -file reports/drc.rpt
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| Design : top
@@ -82,7 +82,7 @@ Related violations: <none>
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PDRC-138#1 Warning
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SLICE_PairEqSame_D6D5_WARN
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Luts D6LUT and D5LUT in use in site SLICE_X69Y106 with different equations without A6 pin connected to Global Logic High.
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Luts D6LUT and D5LUT in use in site SLICE_X36Y106 with different equations without A6 pin connected to Global Logic High.
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Related violations: <none>
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RPBF-3#1 Warning

‎fpga/nexys4_ddr/reports/io.rpt

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Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
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----------------------------------------------------------------------------------------------------------------------------------------------------------
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| Tool Version : Vivado v.2024.2 (lin64) Build 5239630 Fri Nov 08 22:34:34 MST 2024
4-
| Date : Fri Mar 14 22:22:49 2025
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| Date : Sat Mar 15 01:45:31 2025
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| Host : vader running 64-bit Arch Linux
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| Command : report_io -file reports/io.rpt
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| Design : top
@@ -92,7 +92,7 @@ Table of Contents
9292
| D1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
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| D2 | | High Range | IO_L14N_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
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| D3 | | High Range | IO_L12N_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
95-
| D4 | tx | High Range | IO_L11N_T1_SRCC_35 | TRISTATE | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
95+
| D4 | tx | High Range | IO_L11N_T1_SRCC_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
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| D5 | | High Range | IO_L11P_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
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| D6 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
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| D7 | VGA_B[2] | High Range | IO_L6N_T0_VREF_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |

‎fpga/nexys4_ddr/reports/power.rpt

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@@ -1,7 +1,7 @@
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Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
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-------------------------------------------------------------------------------------------------------------------------------------------------
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| Tool Version : Vivado v.2024.2 (lin64) Build 5239630 Fri Nov 08 22:34:34 MST 2024
4-
| Date : Fri Mar 14 22:23:09 2025
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| Date : Sat Mar 15 01:45:51 2025
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| Host : vader running 64-bit Arch Linux
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| Command : report_power -file reports/power.rpt
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| Design : top
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----------
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+--------------------------+--------------+
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| Total On-Chip Power (W) | 0.215 |
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| Total On-Chip Power (W) | 0.214 |
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| Design Power Budget (W) | Unspecified* |
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| Power Budget Margin (W) | NA |
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| Dynamic (W) | 0.118 |
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| Dynamic (W) | 0.117 |
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| Device Static (W) | 0.097 |
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| Effective TJA (C/W) | 4.6 |
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| Max Ambient (C) | 84.0 |
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| On-Chip | Power (W) | Used | Available | Utilization (%) |
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+--------------------------+-----------+----------+-----------+-----------------+
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| Clocks | <0.001 | 3 | --- | --- |
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| Slice Logic | 0.042 | 20484 | --- | --- |
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| LUT as Logic | 0.033 | 7624 | 63400 | 12.03 |
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| LUT as Distributed RAM | 0.008 | 3744 | 19000 | 19.71 |
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| F7/F8 Muxes | <0.001 | 2920 | 63400 | 4.61 |
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| CARRY4 | <0.001 | 228 | 15850 | 1.44 |
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| Register | <0.001 | 4572 | 126800 | 3.61 |
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| Slice Logic | 0.043 | 20922 | --- | --- |
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| LUT as Logic | 0.033 | 7844 | 63400 | 12.37 |
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| LUT as Distributed RAM | 0.008 | 3756 | 19000 | 19.77 |
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| F7/F8 Muxes | <0.001 | 2924 | 63400 | 4.61 |
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| CARRY4 | <0.001 | 236 | 15850 | 1.49 |
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| Register | <0.001 | 4763 | 126800 | 3.76 |
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| BUFG | <0.001 | 1 | 32 | 3.13 |
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| Others | 0.000 | 33 | --- | --- |
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| Signals | 0.068 | 11941 | --- | --- |
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| Others | 0.000 | 42 | --- | --- |
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| Signals | 0.069 | 12232 | --- | --- |
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| DSPs | 0.002 | 4 | 240 | 1.67 |
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| I/O | 0.005 | 41 | 210 | 19.52 |
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| I/O | 0.003 | 42 | 210 | 20.00 |
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| Static Power | 0.097 | | | |
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| Total | 0.215 | | | |
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| Total | 0.214 | | | |
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+--------------------------+-----------+----------+-----------+-----------------+
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+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
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| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A) | Margin (A) |
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+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
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| Vccint | 1.000 | 0.128 | 0.113 | 0.015 | NA | Unspecified | NA |
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| Vccint | 1.000 | 0.129 | 0.114 | 0.015 | NA | Unspecified | NA |
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| Vccaux | 1.800 | 0.018 | 0.000 | 0.018 | NA | Unspecified | NA |
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| Vcco33 | 3.300 | 0.005 | 0.001 | 0.004 | NA | Unspecified | NA |
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| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
@@ -141,17 +141,15 @@ Table of Contents
141141
3.1 By Hierarchy
142142
----------------
143143

144-
+--------------------+-----------+
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| Name | Power (W) |
146-
+--------------------+-----------+
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| top | 0.118 |
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| JA_IOBUF[0]_inst | 0.001 |
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| JA_IOBUF[1]_inst | 0.001 |
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| SOC | 0.109 |
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| Memory | 0.001 |
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| Processor | 0.107 |
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| DCache | 0.002 |
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| N1 | 0.104 |
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+--------------------+-----------+
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+---------------+-----------+
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| Name | Power (W) |
146+
+---------------+-----------+
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| top | 0.117 |
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| SOC | 0.110 |
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| Memory | 0.002 |
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| Processor | 0.106 |
151+
| DCache | 0.002 |
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| N1 | 0.103 |
153+
+---------------+-----------+
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‎fpga/nexys4_ddr/reports/route_status.rpt

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Design Route Status
22
: # nets :
33
------------------------------------------- : ----------- :
4-
# of logical nets.......................... : 21444 :
5-
# of nets not needing routing.......... : 9499 :
6-
# of internally routed nets........ : 9211 :
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# of nets with no loads............ : 288 :
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# of routable nets..................... : 11945 :
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# of fully routed nets............. : 11945 :
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# of logical nets.......................... : 21903 :
5+
# of nets not needing routing.......... : 9667 :
6+
# of internally routed nets........ : 9371 :
7+
# of nets with no loads............ : 296 :
8+
# of routable nets..................... : 12236 :
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# of fully routed nets............. : 12236 :
1010
# of nets with routing errors.......... : 0 :
1111
------------------------------------------- : ----------- :
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