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  - A PAINLESS GUIDE TO CRC ERROR DETECTION ALGORITHMS.pdf
  - ASIC&FPGA设计流程.md
  - CDC--讲师卢子威.pptx
  - CDC总结.md
  - Constraining_Designs_for_Synthesis_and_Timing_Analysis.pdf
  - CrossClockDomain_design.pdf
  - DFT基础.pdf
  - FPGA&ASIC笔面试题船新版本.pdf
  - FPGA&数字IC开发工程师笔试116题.pdf
  - FPGA深度解析.pdf
  - FPGA相关知识.pdf
  - FPGA设计与验证流程.md
  - H-Verilog典型电路设计.pdf
  - Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill.pdf
  - RISC-V手册ch.pdf
  - Simulation and Synthesis Techniques for Asynchronous FIFO Design with Asynchronous Pointer Comparisons.pdf
  - Simulation and Synthesis Techniques for Asynchronous FIFO Design.pdf
  - SoC设计方法与实现_第3版.pdf
  - SystemVerilog验证.pdf
  - The_Art_of_Hardware_Architecture.pdf
  - UVM实战卷Ⅰ.pdf
  - Verilog HDL程序设计-135例.pdf
  - Verilog Nonblocking Assignments With Delays,Myths & Mysteries.pdf
  - Verilog_HDL_那些事儿_时序篇v2.pdf
  - c_ug1292-ultrafast-timing-closure-quick-reference.pdf
  - fifodepthcalculationmadeeasy2.pdf
  - serdes知识讲解.pdf
  - 低功耗.pdf
  - 低功耗笔记.md
  - 实现任意深度异步FIFO的方法及系统.pdf
  - 师兄笔记.pdf
  - 建立时间保持时间.md
  - 异步FIFO.md
  - 异步FIFO面试题.md
  - 插值代码分析.pdf
  - 数字IC面试题.pdf
  - 数字电路基础知识修改版2017_SK.txt
  - 时序约束整理.md
  - 波形捕获率.md
  - 深入浅出数字信号处理.pdf
  - 深度不是2的幂的异步FIFO存储器设计.pdf
  - 硬件架构的艺术.pdf
  - 综合与时序分析的设计约束.pdf
  - 跨时钟域处理3大方法揭秘.pdf
  - 跨越鸿沟_同步世界中的异步信号.pdf
  - 轻松实现高速串行.pdf
  - 逻辑问题汇总.xmind
  - 逻辑问题汇总整理.md
  - 面试题目总结.md
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