diff --git a/CodeEmitter/CodeEmitter/SVEOps.inl b/CodeEmitter/CodeEmitter/SVEOps.inl
index 573ae613b1..27997798ea 100644
--- a/CodeEmitter/CodeEmitter/SVEOps.inl
+++ b/CodeEmitter/CodeEmitter/SVEOps.inl
@@ -5029,7 +5029,7 @@ private:
   void SVE2IntegerMultiplyLong(uint32_t SUT, SubRegSize size, ZRegister zd, ZRegister zn, ZRegister zm) {
     // PMULLB and PMULLT support the use of 128-bit element sizes (with the SVE2PMULL128 extension)
     if (SUT == 0b010 || SUT == 0b011) {
-      LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit, "Can't use 8-bit element size");
+      LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit && size != SubRegSize::i32Bit, "Can't use 8-bit or 32-bit element size");
 
       // 128-bit variant is encoded as if it were 8-bit (0b00)
       if (size == SubRegSize::i128Bit) {
diff --git a/External/vixl b/External/vixl
index d7129872f0..84bc10c107 160000
--- a/External/vixl
+++ b/External/vixl
@@ -1 +1 @@
-Subproject commit d7129872f0e993404642de52b706651e270bff9a
+Subproject commit 84bc10c107b03ffdb5f7a7afb35f6d12618a27c5
diff --git a/FEXCore/unittests/Emitter/SVE_Tests.cpp b/FEXCore/unittests/Emitter/SVE_Tests.cpp
index 88360835be..1cb6957070 100644
--- a/FEXCore/unittests/Emitter/SVE_Tests.cpp
+++ b/FEXCore/unittests/Emitter/SVE_Tests.cpp
@@ -2963,12 +2963,12 @@ TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE2 integer multiply long") {
 
   // TEST_SINGLE(pmullb(SubRegSize::i8Bit, ZReg::z30, ZReg::z29, ZReg::z28), "pmullb z30.b, z29.b, z28.b");
   TEST_SINGLE(pmullb(SubRegSize::i16Bit, ZReg::z30, ZReg::z29, ZReg::z28), "pmullb z30.h, z29.b, z28.b");
-  TEST_SINGLE(pmullb(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, ZReg::z28), "pmullb z30.s, z29.h, z28.h");
+  // TEST_SINGLE(pmullb(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, ZReg::z28), "pmullb z30.s, z29.h, z28.h");
   TEST_SINGLE(pmullb(SubRegSize::i64Bit, ZReg::z30, ZReg::z29, ZReg::z28), "pmullb z30.d, z29.s, z28.s");
 
   // TEST_SINGLE(pmullt(SubRegSize::i8Bit, ZReg::z30, ZReg::z29, ZReg::z28), "pmullt z30.b, z29.b, z28.b");
   TEST_SINGLE(pmullt(SubRegSize::i16Bit, ZReg::z30, ZReg::z29, ZReg::z28), "pmullt z30.h, z29.b, z28.b");
-  TEST_SINGLE(pmullt(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, ZReg::z28), "pmullt z30.s, z29.h, z28.h");
+  // TEST_SINGLE(pmullt(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, ZReg::z28), "pmullt z30.s, z29.h, z28.h");
   TEST_SINGLE(pmullt(SubRegSize::i64Bit, ZReg::z30, ZReg::z29, ZReg::z28), "pmullt z30.d, z29.s, z28.s");
 
   // TEST_SINGLE(smullb(SubRegSize::i8Bit, ZReg::z30, ZReg::z29, ZReg::z28), "smullb z30.b, z29.b, z28.b");
diff --git a/FEXCore/unittests/Emitter/System_Tests.cpp b/FEXCore/unittests/Emitter/System_Tests.cpp
index 19899e77b0..1935c2258f 100644
--- a/FEXCore/unittests/Emitter/System_Tests.cpp
+++ b/FEXCore/unittests/Emitter/System_Tests.cpp
@@ -110,15 +110,14 @@ TEST_CASE_METHOD(TestDisassembler, "Emitter: System: Barriers") {
 
   TEST_SINGLE(isb(), "isb");
 
-  // vixl has a decoding bug claiming these are system level instructions.
-  TEST_SINGLE(sb(), "sb (System)");
-  TEST_SINGLE(tcommit(), "tcommit (System)");
+  TEST_SINGLE(sb(), "sb");
+  TEST_SINGLE(tcommit(), "tcommit");
 }
 TEST_CASE_METHOD(TestDisassembler, "Emitter: System: System register move") {
   // vixl doesn't have decoding for a bunch of these.
   // Also most of these aren't writeable from el0, just testing the encoding.
   TEST_SINGLE(msr(SystemRegister::CTR_EL0, Reg::r30), "msr S3_3_c0_c0_1, x30");
-  TEST_SINGLE(msr(SystemRegister::DCZID_EL0, Reg::r30), "msr S3_3_c0_c0_7, x30");
+  TEST_SINGLE(msr(SystemRegister::DCZID_EL0, Reg::r30), "msr dczid_el0, x30");
   TEST_SINGLE(msr(SystemRegister::TPIDR_EL0, Reg::r30), "msr S3_3_c13_c0_2, x30");
   TEST_SINGLE(msr(SystemRegister::RNDR, Reg::r30), "msr rndr, x30");
   TEST_SINGLE(msr(SystemRegister::RNDRRS, Reg::r30), "msr rndrrs, x30");
@@ -129,7 +128,7 @@ TEST_CASE_METHOD(TestDisassembler, "Emitter: System: System register move") {
   TEST_SINGLE(msr(SystemRegister::CNTVCT_EL0, Reg::r30), "msr S3_3_c14_c0_2, x30");
 
   TEST_SINGLE(mrs(Reg::r30, SystemRegister::CTR_EL0), "mrs x30, S3_3_c0_c0_1");
-  TEST_SINGLE(mrs(Reg::r30, SystemRegister::DCZID_EL0), "mrs x30, S3_3_c0_c0_7");
+  TEST_SINGLE(mrs(Reg::r30, SystemRegister::DCZID_EL0), "mrs x30, dczid_el0");
   TEST_SINGLE(mrs(Reg::r30, SystemRegister::TPIDR_EL0), "mrs x30, S3_3_c13_c0_2");
   TEST_SINGLE(mrs(Reg::r30, SystemRegister::RNDR), "mrs x30, rndr");
   TEST_SINGLE(mrs(Reg::r30, SystemRegister::RNDRRS), "mrs x30, rndrrs");
diff --git a/Source/Common/HostFeatures.cpp b/Source/Common/HostFeatures.cpp
index e3de6a0eea..7098fcc8d2 100644
--- a/Source/Common/HostFeatures.cpp
+++ b/Source/Common/HostFeatures.cpp
@@ -543,10 +543,14 @@ FEXCore::HostFeatures FetchHostFeatures(FEX::CPUFeatures& Features, bool Support
 #endif
 
 #ifdef VIXL_SIMULATOR
-  // simulator doesn't support dc(ZVA)
-  HostFeatures.SupportsCLZERO = false;
-  // Simulator doesn't support SHA
-  HostFeatures.SupportsSHA = false;
+  // simulator has a hardcoded ZVA size of 64-bytes.
+  HostFeatures.SupportsCLZERO = true;
+  HostFeatures.SupportsAES = true;
+  HostFeatures.SupportsCRC = true;
+  HostFeatures.SupportsAVX = true;
+  HostFeatures.SupportsSHA = true;
+  HostFeatures.SupportsPMULL_128Bit = true;
+  HostFeatures.SupportsAES256 = true;
 #else
   // Check if we can support cacheline clears
   uint32_t DCZID = GetDCZID();
diff --git a/unittests/ASM/Disabled_Tests_Simulator b/unittests/ASM/Disabled_Tests_Simulator
index cb2d79f507..020183ecc3 100644
--- a/unittests/ASM/Disabled_Tests_Simulator
+++ b/unittests/ASM/Disabled_Tests_Simulator
@@ -10,27 +10,13 @@ Test_X87/precision_test_neg_ftan.asm
 Test_X87/precision_test_neg_fatan.asm
 Test_X87/precision_test_neg_fyl2xp1.asm
 
-# AES unsupported in simulator
-Test_H0F38/66_DB.asm
-Test_H0F38/66_DC.asm
-Test_H0F38/66_DD.asm
-Test_H0F38/66_DE.asm
-Test_H0F38/66_DF.asm
-Test_H0F3A/0_66_DF.asm
+# AES and vpclmul unsupported in 256-bit SVE currently
 Test_VEX/vaesdec.asm
 Test_VEX/vaesdeclast.asm
-Test_VEX/vaesenc.asm
-Test_VEX/vaesenclast.asm
-Test_VEX/vaesimc.asm
 Test_VEX/vaesdec256.asm
 Test_VEX/vaesdeclast256.asm
 Test_VEX/vaesenc256.asm
 Test_VEX/vaesenclast256.asm
-Test_VEX/vaeskeygenassist.asm
-
-# PCMUL considered to be part of crypto operations. Simulator doesn't support this.
-Test_H0F3A/pclmulqdq.asm
-Test_VEX/vpclmulqdq.asm
 Test_VEX/vpclmulqdq_256.asm
 
 # Simulator can't handle self-modifying code
diff --git a/unittests/InstructionCountCI/AVX128/VEX_map2.json b/unittests/InstructionCountCI/AVX128/VEX_map2.json
index 52650dd084..6ef4af6b3b 100644
--- a/unittests/InstructionCountCI/AVX128/VEX_map2.json
+++ b/unittests/InstructionCountCI/AVX128/VEX_map2.json
@@ -5920,7 +5920,7 @@
         "Map 2 0b01 0xdb 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "unimplemented (Unimplemented)",
+        "aesimc v16.16b, v17.16b",
         "movi v2.2d, #0x0",
         "str q2, [x28, #16]"
       ]
@@ -5933,8 +5933,8 @@
       "ExpectedArm64ASM": [
         "movi v2.2d, #0x0",
         "mov v0.16b, v17.16b",
-        "unimplemented (Unimplemented)",
-        "unimplemented (Unimplemented)",
+        "aese v0.16b, v2.16b",
+        "aesmc v0.16b, v0.16b",
         "eor v16.16b, v0.16b, v18.16b",
         "str q2, [x28, #16]"
       ]
@@ -5949,12 +5949,12 @@
         "ldr q3, [x28, #32]",
         "ldr q4, [x28, #48]",
         "mov v0.16b, v17.16b",
-        "unimplemented (Unimplemented)",
-        "unimplemented (Unimplemented)",
+        "aese v0.16b, v2.16b",
+        "aesmc v0.16b, v0.16b",
         "eor v16.16b, v0.16b, v18.16b",
         "mov v0.16b, v3.16b",
-        "unimplemented (Unimplemented)",
-        "unimplemented (Unimplemented)",
+        "aese v0.16b, v2.16b",
+        "aesmc v0.16b, v0.16b",
         "eor v2.16b, v0.16b, v4.16b",
         "str q2, [x28, #16]"
       ]
@@ -5967,7 +5967,7 @@
       "ExpectedArm64ASM": [
         "movi v2.2d, #0x0",
         "mov v0.16b, v17.16b",
-        "unimplemented (Unimplemented)",
+        "aese v0.16b, v2.16b",
         "eor v16.16b, v0.16b, v18.16b",
         "str q2, [x28, #16]"
       ]
@@ -5982,10 +5982,10 @@
         "ldr q3, [x28, #32]",
         "ldr q4, [x28, #48]",
         "mov v0.16b, v17.16b",
-        "unimplemented (Unimplemented)",
+        "aese v0.16b, v2.16b",
         "eor v16.16b, v0.16b, v18.16b",
         "mov v0.16b, v3.16b",
-        "unimplemented (Unimplemented)",
+        "aese v0.16b, v2.16b",
         "eor v2.16b, v0.16b, v4.16b",
         "str q2, [x28, #16]"
       ]
@@ -5998,8 +5998,8 @@
       "ExpectedArm64ASM": [
         "movi v2.2d, #0x0",
         "mov v0.16b, v17.16b",
-        "unimplemented (Unimplemented)",
-        "unimplemented (Unimplemented)",
+        "aesd v0.16b, v2.16b",
+        "aesimc v0.16b, v0.16b",
         "eor v16.16b, v0.16b, v18.16b",
         "str q2, [x28, #16]"
       ]
@@ -6014,12 +6014,12 @@
         "ldr q3, [x28, #32]",
         "ldr q4, [x28, #48]",
         "mov v0.16b, v17.16b",
-        "unimplemented (Unimplemented)",
-        "unimplemented (Unimplemented)",
+        "aesd v0.16b, v2.16b",
+        "aesimc v0.16b, v0.16b",
         "eor v16.16b, v0.16b, v18.16b",
         "mov v0.16b, v3.16b",
-        "unimplemented (Unimplemented)",
-        "unimplemented (Unimplemented)",
+        "aesd v0.16b, v2.16b",
+        "aesimc v0.16b, v0.16b",
         "eor v2.16b, v0.16b, v4.16b",
         "str q2, [x28, #16]"
       ]
@@ -6032,7 +6032,7 @@
       "ExpectedArm64ASM": [
         "movi v2.2d, #0x0",
         "mov v0.16b, v17.16b",
-        "unimplemented (Unimplemented)",
+        "aesd v0.16b, v2.16b",
         "eor v16.16b, v0.16b, v18.16b",
         "str q2, [x28, #16]"
       ]
@@ -6047,10 +6047,10 @@
         "ldr q3, [x28, #32]",
         "ldr q4, [x28, #48]",
         "mov v0.16b, v17.16b",
-        "unimplemented (Unimplemented)",
+        "aesd v0.16b, v2.16b",
         "eor v16.16b, v0.16b, v18.16b",
         "mov v0.16b, v3.16b",
-        "unimplemented (Unimplemented)",
+        "aesd v0.16b, v2.16b",
         "eor v2.16b, v0.16b, v4.16b",
         "str q2, [x28, #16]"
       ]
diff --git a/unittests/InstructionCountCI/AVX128/VEX_map3.json b/unittests/InstructionCountCI/AVX128/VEX_map3.json
index 3bba870d4a..49264bb144 100644
--- a/unittests/InstructionCountCI/AVX128/VEX_map3.json
+++ b/unittests/InstructionCountCI/AVX128/VEX_map3.json
@@ -4024,7 +4024,7 @@
         "movi v2.2d, #0x0",
         "ldr q3, [x28, #2576]",
         "mov v16.16b, v17.16b",
-        "unimplemented (Unimplemented)",
+        "aese v16.16b, v2.16b",
         "tbl v16.16b, {v16.16b}, v3.16b",
         "str q2, [x28, #16]"
       ]
@@ -4038,7 +4038,7 @@
         "movi v2.2d, #0x0",
         "ldr q3, [x28, #2576]",
         "mov v16.16b, v17.16b",
-        "unimplemented (Unimplemented)",
+        "aese v16.16b, v2.16b",
         "tbl v16.16b, {v16.16b}, v3.16b",
         "mov x0, #0xff00000000",
         "dup v1.2d, x0",
diff --git a/unittests/InstructionCountCI/Crypto/H0F38.json b/unittests/InstructionCountCI/Crypto/H0F38.json
index 01f617d682..5d042ea792 100644
--- a/unittests/InstructionCountCI/Crypto/H0F38.json
+++ b/unittests/InstructionCountCI/Crypto/H0F38.json
@@ -18,7 +18,7 @@
       ],
       "ExpectedArm64ASM": [
         "dup v2.4s, v16.s[3]",
-        "unimplemented (Unimplemented)",
+        "sha1h s2, s2",
         "dup v2.4s, v2.s[0]",
         "add v2.4s, v17.4s, v2.4s",
         "mov v16.16b, v17.16b",
@@ -35,7 +35,7 @@
         "ext v2.16b, v2.16b, v2.16b, #8",
         "rev64 v3.4s, v17.4s",
         "ext v3.16b, v3.16b, v3.16b, #8",
-        "unimplemented (Unimplemented)",
+        "sha1su1 v2.4s, v3.4s",
         "rev64 v2.4s, v2.4s",
         "ext v16.16b, v2.16b, v2.16b, #8"
       ]
@@ -46,7 +46,7 @@
         "0x66 0x0f 0x38 0xcc"
       ],
       "ExpectedArm64ASM": [
-        "unimplemented (Unimplemented)"
+        "sha256su0 v16.4s, v17.4s"
       ]
     },
     "sha256msg2 xmm0, xmm1": {
@@ -59,7 +59,7 @@
         "dup v3.4s, v16.s[3]",
         "zip2 v3.2d, v3.2d, v17.2d",
         "movi v16.2d, #0x0",
-        "unimplemented (Unimplemented)"
+        "sha256su1 v16.4s, v2.4s, v3.4s"
       ]
     },
     "aesimc xmm0, xmm1": {
@@ -68,7 +68,7 @@
         "0x66 0x0f 0x38 0xdb"
       ],
       "ExpectedArm64ASM": [
-        "unimplemented (Unimplemented)"
+        "aesimc v16.16b, v17.16b"
       ]
     },
     "aesenc xmm0, xmm1": {
@@ -78,8 +78,8 @@
       ],
       "ExpectedArm64ASM": [
         "movi v2.2d, #0x0",
-        "unimplemented (Unimplemented)",
-        "unimplemented (Unimplemented)",
+        "aese v16.16b, v2.16b",
+        "aesmc v16.16b, v16.16b",
         "eor v16.16b, v16.16b, v17.16b"
       ]
     },
@@ -90,7 +90,7 @@
       ],
       "ExpectedArm64ASM": [
         "movi v2.2d, #0x0",
-        "unimplemented (Unimplemented)",
+        "aese v16.16b, v2.16b",
         "eor v16.16b, v16.16b, v17.16b"
       ]
     },
@@ -101,8 +101,8 @@
       ],
       "ExpectedArm64ASM": [
         "movi v2.2d, #0x0",
-        "unimplemented (Unimplemented)",
-        "unimplemented (Unimplemented)",
+        "aesd v16.16b, v2.16b",
+        "aesimc v16.16b, v16.16b",
         "eor v16.16b, v16.16b, v17.16b"
       ]
     },
@@ -113,7 +113,7 @@
       ],
       "ExpectedArm64ASM": [
         "movi v2.2d, #0x0",
-        "unimplemented (Unimplemented)",
+        "aesd v16.16b, v2.16b",
         "eor v16.16b, v16.16b, v17.16b"
       ]
     },
diff --git a/unittests/InstructionCountCI/Crypto/H0F3A.json b/unittests/InstructionCountCI/Crypto/H0F3A.json
index f0d3aad456..479a930353 100644
--- a/unittests/InstructionCountCI/Crypto/H0F3A.json
+++ b/unittests/InstructionCountCI/Crypto/H0F3A.json
@@ -58,7 +58,7 @@
         "ldr q2, [x28, #2576]",
         "movi v3.2d, #0x0",
         "mov v16.16b, v17.16b",
-        "unimplemented (Unimplemented)",
+        "aese v16.16b, v3.16b",
         "tbl v16.16b, {v16.16b}, v2.16b"
       ]
     },
@@ -71,7 +71,7 @@
         "ldr q2, [x28, #2576]",
         "movi v3.2d, #0x0",
         "mov v16.16b, v17.16b",
-        "unimplemented (Unimplemented)",
+        "aese v16.16b, v3.16b",
         "tbl v16.16b, {v16.16b}, v2.16b",
         "mov x0, #0xff00000000",
         "dup v1.2d, x0",
@@ -91,7 +91,7 @@
         "rev64 v5.4s, v17.4s",
         "ext v5.16b, v5.16b, v5.16b, #8",
         "add v2.4s, v5.4s, v2.4s",
-        "unimplemented (Unimplemented)",
+        "sha1c q4, s3, v2.4s",
         "rev64 v2.4s, v4.4s",
         "ext v16.16b, v2.16b, v2.16b, #8"
       ]
@@ -109,7 +109,7 @@
         "rev64 v5.4s, v17.4s",
         "ext v5.16b, v5.16b, v5.16b, #8",
         "add v2.4s, v5.4s, v2.4s",
-        "unimplemented (Unimplemented)",
+        "sha1p q4, s3, v2.4s",
         "rev64 v2.4s, v4.4s",
         "ext v16.16b, v2.16b, v2.16b, #8"
       ]
@@ -127,7 +127,7 @@
         "rev64 v5.4s, v17.4s",
         "ext v5.16b, v5.16b, v5.16b, #8",
         "add v2.4s, v5.4s, v2.4s",
-        "unimplemented (Unimplemented)",
+        "sha1m q4, s3, v2.4s",
         "rev64 v2.4s, v4.4s",
         "ext v16.16b, v2.16b, v2.16b, #8"
       ]
@@ -145,7 +145,7 @@
         "rev64 v5.4s, v17.4s",
         "ext v5.16b, v5.16b, v5.16b, #8",
         "add v2.4s, v5.4s, v2.4s",
-        "unimplemented (Unimplemented)",
+        "sha1p q4, s3, v2.4s",
         "rev64 v2.4s, v4.4s",
         "ext v16.16b, v2.16b, v2.16b, #8"
       ]
diff --git a/unittests/InstructionCountCI/FEXOpt/libnss.json b/unittests/InstructionCountCI/FEXOpt/libnss.json
index 9e0883beca..f84a4d59b5 100644
--- a/unittests/InstructionCountCI/FEXOpt/libnss.json
+++ b/unittests/InstructionCountCI/FEXOpt/libnss.json
@@ -225,7 +225,7 @@
         "tbl v24.16b, {v24.16b}, v2.16b",
         "ldr q16, [x29, x20, sxtx]",
         "add v16.4s, v16.4s, v24.4s",
-        "unimplemented (Unimplemented)",
+        "sha256su0 v24.4s, v23.4s",
         "mov w21, v19.s[1]",
         "mov w22, v19.s[0]",
         "mov w23, v20.s[1]",
@@ -348,9 +348,9 @@
         "dup v3.4s, v24.s[3]",
         "zip2 v3.2d, v3.2d, v21.2d",
         "movi v24.2d, #0x0",
-        "unimplemented (Unimplemented)",
+        "sha256su1 v24.4s, v2.4s, v3.4s",
         "add v16.4s, v16.4s, v23.4s",
-        "unimplemented (Unimplemented)",
+        "sha256su0 v23.4s, v22.4s",
         "mov w21, v17.s[1]",
         "mov w22, v17.s[0]",
         "mov w23, v20.s[1]",
@@ -473,9 +473,9 @@
         "dup v3.4s, v23.s[3]",
         "zip2 v3.2d, v3.2d, v24.2d",
         "movi v23.2d, #0x0",
-        "unimplemented (Unimplemented)",
+        "sha256su1 v23.4s, v2.4s, v3.4s",
         "add v16.4s, v16.4s, v22.4s",
-        "unimplemented (Unimplemented)",
+        "sha256su0 v22.4s, v21.4s",
         "mov w21, v17.s[1]",
         "mov w22, v17.s[0]",
         "mov w23, v20.s[1]",
@@ -598,9 +598,9 @@
         "dup v3.4s, v22.s[3]",
         "zip2 v3.2d, v3.2d, v23.2d",
         "movi v22.2d, #0x0",
-        "unimplemented (Unimplemented)",
+        "sha256su1 v22.4s, v2.4s, v3.4s",
         "add v16.4s, v16.4s, v21.4s",
-        "unimplemented (Unimplemented)",
+        "sha256su0 v21.4s, v24.4s",
         "mov w21, v17.s[1]",
         "mov w22, v17.s[0]",
         "mov w23, v20.s[1]",
@@ -723,9 +723,9 @@
         "dup v3.4s, v21.s[3]",
         "zip2 v3.2d, v3.2d, v22.2d",
         "movi v21.2d, #0x0",
-        "unimplemented (Unimplemented)",
+        "sha256su1 v21.4s, v2.4s, v3.4s",
         "add v16.4s, v16.4s, v24.4s",
-        "unimplemented (Unimplemented)",
+        "sha256su0 v24.4s, v23.4s",
         "mov w21, v17.s[1]",
         "mov w22, v17.s[0]",
         "mov w23, v20.s[1]",
@@ -848,9 +848,9 @@
         "dup v3.4s, v24.s[3]",
         "zip2 v3.2d, v3.2d, v21.2d",
         "movi v24.2d, #0x0",
-        "unimplemented (Unimplemented)",
+        "sha256su1 v24.4s, v2.4s, v3.4s",
         "add v16.4s, v16.4s, v23.4s",
-        "unimplemented (Unimplemented)",
+        "sha256su0 v23.4s, v22.4s",
         "mov w21, v17.s[1]",
         "mov w22, v17.s[0]",
         "mov w23, v20.s[1]",
@@ -973,9 +973,9 @@
         "dup v3.4s, v23.s[3]",
         "zip2 v3.2d, v3.2d, v24.2d",
         "movi v23.2d, #0x0",
-        "unimplemented (Unimplemented)",
+        "sha256su1 v23.4s, v2.4s, v3.4s",
         "add v16.4s, v16.4s, v22.4s",
-        "unimplemented (Unimplemented)",
+        "sha256su0 v22.4s, v21.4s",
         "mov w21, v17.s[1]",
         "mov w22, v17.s[0]",
         "mov w23, v20.s[1]",
@@ -1098,9 +1098,9 @@
         "dup v3.4s, v22.s[3]",
         "zip2 v3.2d, v3.2d, v23.2d",
         "movi v22.2d, #0x0",
-        "unimplemented (Unimplemented)",
+        "sha256su1 v22.4s, v2.4s, v3.4s",
         "add v16.4s, v16.4s, v21.4s",
-        "unimplemented (Unimplemented)",
+        "sha256su0 v21.4s, v24.4s",
         "mov w21, v17.s[1]",
         "mov w22, v17.s[0]",
         "mov w23, v20.s[1]",
@@ -1223,9 +1223,9 @@
         "dup v3.4s, v21.s[3]",
         "zip2 v3.2d, v3.2d, v22.2d",
         "movi v21.2d, #0x0",
-        "unimplemented (Unimplemented)",
+        "sha256su1 v21.4s, v2.4s, v3.4s",
         "add v16.4s, v16.4s, v24.4s",
-        "unimplemented (Unimplemented)",
+        "sha256su0 v24.4s, v23.4s",
         "mov w21, v17.s[1]",
         "mov w22, v17.s[0]",
         "mov w23, v20.s[1]",
@@ -1348,9 +1348,9 @@
         "dup v3.4s, v24.s[3]",
         "zip2 v3.2d, v3.2d, v21.2d",
         "movi v24.2d, #0x0",
-        "unimplemented (Unimplemented)",
+        "sha256su1 v24.4s, v2.4s, v3.4s",
         "add v16.4s, v16.4s, v23.4s",
-        "unimplemented (Unimplemented)",
+        "sha256su0 v23.4s, v22.4s",
         "mov w21, v17.s[1]",
         "mov w22, v17.s[0]",
         "mov w23, v20.s[1]",
@@ -1473,9 +1473,9 @@
         "dup v3.4s, v23.s[3]",
         "zip2 v3.2d, v3.2d, v24.2d",
         "movi v23.2d, #0x0",
-        "unimplemented (Unimplemented)",
+        "sha256su1 v23.4s, v2.4s, v3.4s",
         "add v16.4s, v16.4s, v22.4s",
-        "unimplemented (Unimplemented)",
+        "sha256su0 v22.4s, v21.4s",
         "mov w21, v17.s[1]",
         "mov w22, v17.s[0]",
         "mov w23, v20.s[1]",
@@ -1598,9 +1598,9 @@
         "dup v3.4s, v22.s[3]",
         "zip2 v3.2d, v3.2d, v23.2d",
         "movi v22.2d, #0x0",
-        "unimplemented (Unimplemented)",
+        "sha256su1 v22.4s, v2.4s, v3.4s",
         "add v16.4s, v16.4s, v21.4s",
-        "unimplemented (Unimplemented)",
+        "sha256su0 v21.4s, v24.4s",
         "mov w21, v17.s[1]",
         "mov w22, v17.s[0]",
         "mov w23, v20.s[1]",
@@ -1725,7 +1725,7 @@
         "dup v3.4s, v21.s[3]",
         "zip2 v3.2d, v3.2d, v22.2d",
         "movi v21.2d, #0x0",
-        "unimplemented (Unimplemented)",
+        "sha256su1 v21.4s, v2.4s, v3.4s",
         "ldr q2, [x29, x20, sxtx]",
         "add v22.4s, v22.4s, v2.4s",
         "ldr q2, [x29, x20, sxtx]",
diff --git a/unittests/InstructionCountCI/VEX_map2.json b/unittests/InstructionCountCI/VEX_map2.json
index fbe27087eb..7a7602435d 100644
--- a/unittests/InstructionCountCI/VEX_map2.json
+++ b/unittests/InstructionCountCI/VEX_map2.json
@@ -4813,7 +4813,7 @@
         "Map 2 0b01 0xdb 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "unimplemented (Unimplemented)"
+        "aesimc v16.16b, v17.16b"
       ]
     },
     "vaesenc xmm0, xmm1, xmm2": {
@@ -4824,8 +4824,8 @@
       "ExpectedArm64ASM": [
         "movi v2.2d, #0x0",
         "mov v0.16b, v17.16b",
-        "unimplemented (Unimplemented)",
-        "unimplemented (Unimplemented)",
+        "aese v0.16b, v2.16b",
+        "aesmc v0.16b, v0.16b",
         "eor v16.16b, v0.16b, v18.16b"
       ]
     },
@@ -4844,7 +4844,7 @@
       "ExpectedArm64ASM": [
         "movi v2.2d, #0x0",
         "mov v0.16b, v17.16b",
-        "unimplemented (Unimplemented)",
+        "aese v0.16b, v2.16b",
         "eor v16.16b, v0.16b, v18.16b"
       ]
     },
@@ -4863,8 +4863,8 @@
       "ExpectedArm64ASM": [
         "movi v2.2d, #0x0",
         "mov v0.16b, v17.16b",
-        "unimplemented (Unimplemented)",
-        "unimplemented (Unimplemented)",
+        "aesd v0.16b, v2.16b",
+        "aesimc v0.16b, v0.16b",
         "eor v16.16b, v0.16b, v18.16b"
       ]
     },
@@ -4883,7 +4883,7 @@
       "ExpectedArm64ASM": [
         "movi v2.2d, #0x0",
         "mov v0.16b, v17.16b",
-        "unimplemented (Unimplemented)",
+        "aesd v0.16b, v2.16b",
         "eor v16.16b, v0.16b, v18.16b"
       ]
     },
diff --git a/unittests/InstructionCountCI/VEX_map3.json b/unittests/InstructionCountCI/VEX_map3.json
index 7f3a344aaf..43ea0fb206 100644
--- a/unittests/InstructionCountCI/VEX_map3.json
+++ b/unittests/InstructionCountCI/VEX_map3.json
@@ -5375,7 +5375,7 @@
         "ldr q2, [x28, #2576]",
         "movi v3.2d, #0x0",
         "mov v16.16b, v17.16b",
-        "unimplemented (Unimplemented)",
+        "aese v16.16b, v3.16b",
         "tbl v16.16b, {v16.16b}, v2.16b"
       ]
     },
@@ -5388,7 +5388,7 @@
         "ldr q2, [x28, #2576]",
         "movi v3.2d, #0x0",
         "mov v16.16b, v17.16b",
-        "unimplemented (Unimplemented)",
+        "aese v16.16b, v3.16b",
         "tbl v16.16b, {v16.16b}, v2.16b",
         "mov x0, #0xff00000000",
         "dup v1.2d, x0",