From d448976b3cc7399d68e759f0158f4a23cd561414 Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Sat, 22 Feb 2025 04:53:47 -0800 Subject: [PATCH] InstcountCI: Update --- .../InstructionCountCI/AVX128/VEX_map1.json | 112 ++++---- .../InstructionCountCI/AVX128/VEX_map2.json | 50 ++-- .../AVX128/VEX_map2_SVE128.json | 48 ++-- .../InstructionCountCI/AVX128/VEX_map3.json | 76 +++--- .../InstructionCountCI/Crypto/H0F3A.json | 252 ++++-------------- unittests/InstructionCountCI/DDD.json | 4 +- .../InstructionCountCI/FlagM/Secondary.json | 2 +- .../FlagM/Secondary_OpSize.json | 2 +- .../InstructionCountCI/FlagM/VEX_map1.json | 2 +- .../FlagM/x87-Crysis2Max-fmodel.json | 2 +- .../FlagM/x87-HalfLife.json | 22 +- .../FlagM/x87-Oblivion.json | 86 +++--- .../FlagM/x87-Psychonauts.json | 30 +-- unittests/InstructionCountCI/FlagM/x87.json | 20 +- unittests/InstructionCountCI/H0F38.json | 2 +- unittests/InstructionCountCI/H0F3A.json | 14 +- .../InstructionCountCI/PrimaryGroup.json | 8 +- unittests/InstructionCountCI/Secondary.json | 32 +-- .../InstructionCountCI/Secondary_OpSize.json | 30 +-- .../InstructionCountCI/Secondary_REP.json | 24 +- .../InstructionCountCI/Secondary_REPNE.json | 26 +- .../Secondary_REPNE_SVE128.json | 4 +- unittests/InstructionCountCI/VEX_map1.json | 48 ++-- unittests/InstructionCountCI/VEX_map2.json | 26 +- unittests/InstructionCountCI/VEX_map3.json | 4 +- unittests/InstructionCountCI/x87.json | 20 +- 26 files changed, 393 insertions(+), 553 deletions(-) diff --git a/unittests/InstructionCountCI/AVX128/VEX_map1.json b/unittests/InstructionCountCI/AVX128/VEX_map1.json index 4feefaefc6..e3304683dd 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map1.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map1.json @@ -505,7 +505,7 @@ ], "ExpectedArm64ASM": [ "ushr v2.4s, v16.4s, #31", - "ldr q3, [x28, #2528]", + "ldr q3, [x28, #2560]", "ushl v2.4s, v2.4s, v3.4s", "addv s2, v2.4s", "mov w4, v2.s[0]" @@ -519,7 +519,7 @@ "ExpectedArm64ASM": [ "ldr q2, [x28, #16]", "ushr v3.4s, v16.4s, #31", - "ldr q4, [x28, #2528]", + "ldr q4, [x28, #2560]", "ushl v3.4s, v3.4s, v4.4s", "addv s3, v3.4s", "mov w20, v3.s[0]", @@ -1168,7 +1168,7 @@ ], "ExpectedArm64ASM": [ "movi v2.2d, #0x0", - "ldr x0, [x28, #2064]", + "ldr x0, [x28, #2096]", "ldr q3, [x0, #16]", "tbl v16.16b, {v17.16b}, v3.16b", "str q2, [x28, #16]" @@ -1181,7 +1181,7 @@ ], "ExpectedArm64ASM": [ "movi v2.2d, #0x0", - "ldr x0, [x28, #2064]", + "ldr x0, [x28, #2096]", "ldr q3, [x0, #32]", "tbl v16.16b, {v17.16b}, v3.16b", "str q2, [x28, #16]" @@ -1194,7 +1194,7 @@ ], "ExpectedArm64ASM": [ "movi v2.2d, #0x0", - "ldr x0, [x28, #2064]", + "ldr x0, [x28, #2096]", "ldr q3, [x0, #48]", "tbl v16.16b, {v17.16b}, v3.16b", "str q2, [x28, #16]" @@ -1219,7 +1219,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x28, #32]", - "ldr x0, [x28, #2064]", + "ldr x0, [x28, #2096]", "ldr q3, [x0, #16]", "tbl v16.16b, {v17.16b}, v3.16b", "tbl v2.16b, {v2.16b}, v3.16b", @@ -1233,7 +1233,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x28, #32]", - "ldr x0, [x28, #2064]", + "ldr x0, [x28, #2096]", "ldr q3, [x0, #32]", "tbl v16.16b, {v17.16b}, v3.16b", "tbl v2.16b, {v2.16b}, v3.16b", @@ -1247,7 +1247,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x28, #32]", - "ldr x0, [x28, #2064]", + "ldr x0, [x28, #2096]", "ldr q3, [x0, #48]", "tbl v16.16b, {v17.16b}, v3.16b", "tbl v2.16b, {v2.16b}, v3.16b", @@ -1272,7 +1272,7 @@ "Map 1 0b10 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2056]", + "ldr x0, [x28, #2088]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b}, v2.16b", "movi v2.2d, #0x0", @@ -1285,7 +1285,7 @@ "Map 1 0b10 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2056]", + "ldr x0, [x28, #2088]", "ldr q2, [x0, #32]", "tbl v16.16b, {v17.16b}, v2.16b", "movi v2.2d, #0x0", @@ -1298,7 +1298,7 @@ "Map 1 0b10 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2056]", + "ldr x0, [x28, #2088]", "ldr q2, [x0, #48]", "tbl v16.16b, {v17.16b}, v2.16b", "movi v2.2d, #0x0", @@ -1326,7 +1326,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x28, #32]", - "ldr x0, [x28, #2056]", + "ldr x0, [x28, #2088]", "ldr q3, [x0, #16]", "tbl v16.16b, {v17.16b}, v3.16b", "tbl v2.16b, {v2.16b}, v3.16b", @@ -1340,7 +1340,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x28, #32]", - "ldr x0, [x28, #2056]", + "ldr x0, [x28, #2088]", "ldr q3, [x0, #32]", "tbl v16.16b, {v17.16b}, v3.16b", "tbl v2.16b, {v2.16b}, v3.16b", @@ -1354,7 +1354,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x28, #32]", - "ldr x0, [x28, #2056]", + "ldr x0, [x28, #2088]", "ldr q3, [x0, #48]", "tbl v16.16b, {v17.16b}, v3.16b", "tbl v2.16b, {v2.16b}, v3.16b", @@ -1379,7 +1379,7 @@ "Map 1 0b11 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2048]", + "ldr x0, [x28, #2080]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b}, v2.16b", "movi v2.2d, #0x0", @@ -1392,7 +1392,7 @@ "Map 1 0b11 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2048]", + "ldr x0, [x28, #2080]", "ldr q2, [x0, #32]", "tbl v16.16b, {v17.16b}, v2.16b", "movi v2.2d, #0x0", @@ -1405,7 +1405,7 @@ "Map 1 0b11 0x70 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2048]", + "ldr x0, [x28, #2080]", "ldr q2, [x0, #48]", "tbl v16.16b, {v17.16b}, v2.16b", "movi v2.2d, #0x0", @@ -1433,7 +1433,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x28, #32]", - "ldr x0, [x28, #2048]", + "ldr x0, [x28, #2080]", "ldr q3, [x0, #16]", "tbl v16.16b, {v17.16b}, v3.16b", "tbl v2.16b, {v2.16b}, v3.16b", @@ -1447,7 +1447,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x28, #32]", - "ldr x0, [x28, #2048]", + "ldr x0, [x28, #2080]", "ldr q3, [x0, #32]", "tbl v16.16b, {v17.16b}, v3.16b", "tbl v2.16b, {v2.16b}, v3.16b", @@ -1461,7 +1461,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x28, #32]", - "ldr x0, [x28, #2048]", + "ldr x0, [x28, #2080]", "ldr q3, [x0, #48]", "tbl v16.16b, {v17.16b}, v3.16b", "tbl v2.16b, {v2.16b}, v3.16b", @@ -2384,7 +2384,7 @@ "Map 1 0b00 0xC6 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2072]", + "ldr x0, [x28, #2104]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b, v18.16b}, v2.16b", "movi v2.2d, #0x0", @@ -2399,7 +2399,7 @@ "ExpectedArm64ASM": [ "ldr q2, [x28, #32]", "ldr q3, [x28, #48]", - "ldr x0, [x28, #2072]", + "ldr x0, [x28, #2104]", "ldr q4, [x0, #16]", "tbl v16.16b, {v17.16b, v18.16b}, v4.16b", "tbl v2.16b, {v2.16b, v3.16b}, v4.16b", @@ -2412,7 +2412,7 @@ "Map 1 0b00 0xC6 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2072]", + "ldr x0, [x28, #2104]", "ldr q2, [x0, #32]", "tbl v16.16b, {v17.16b, v18.16b}, v2.16b", "movi v2.2d, #0x0", @@ -2427,7 +2427,7 @@ "ExpectedArm64ASM": [ "ldr q2, [x28, #32]", "ldr q3, [x28, #48]", - "ldr x0, [x28, #2072]", + "ldr x0, [x28, #2104]", "ldr q4, [x0, #32]", "tbl v16.16b, {v17.16b, v18.16b}, v4.16b", "tbl v2.16b, {v2.16b, v3.16b}, v4.16b", @@ -2440,7 +2440,7 @@ "Map 1 0b00 0xC6 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2072]", + "ldr x0, [x28, #2104]", "ldr q2, [x0, #48]", "tbl v16.16b, {v17.16b, v18.16b}, v2.16b", "movi v2.2d, #0x0", @@ -2455,7 +2455,7 @@ "ExpectedArm64ASM": [ "ldr q2, [x28, #32]", "ldr q3, [x28, #48]", - "ldr x0, [x28, #2072]", + "ldr x0, [x28, #2104]", "ldr q4, [x0, #48]", "tbl v16.16b, {v17.16b, v18.16b}, v4.16b", "tbl v2.16b, {v2.16b, v3.16b}, v4.16b", @@ -2732,7 +2732,7 @@ "ExpectedArm64ASM": [ "fcvtzs w20, s16", "mov w21, #0x80000000", - "ldr s2, [x28, #2784]", + "ldr s2, [x28, #2816]", "mrs x22, nzcv", "fcmp s2, s16", "csel w4, w20, w21, gt", @@ -2747,7 +2747,7 @@ "ExpectedArm64ASM": [ "fcvtzs x20, s16", "mov x21, #0x8000000000000000", - "ldr s2, [x28, #2816]", + "ldr s2, [x28, #2848]", "mrs x22, nzcv", "fcmp s2, s16", "csel x4, x20, x21, gt", @@ -2762,7 +2762,7 @@ "ExpectedArm64ASM": [ "fcvtzs w20, d16", "mov w21, #0x80000000", - "ldr d2, [x28, #2832]", + "ldr d2, [x28, #2864]", "mrs x22, nzcv", "fcmp d2, d16", "csel w4, w20, w21, gt", @@ -2777,7 +2777,7 @@ "ExpectedArm64ASM": [ "fcvtzs x20, d16", "mov x21, #0x8000000000000000", - "ldr d2, [x28, #2864]", + "ldr d2, [x28, #2896]", "mrs x22, nzcv", "fcmp d2, d16", "csel x4, x20, x21, gt", @@ -2793,7 +2793,7 @@ "frinti s2, s16", "fcvtzs w20, s2", "mov w21, #0x80000000", - "ldr s3, [x28, #2784]", + "ldr s3, [x28, #2816]", "mrs x22, nzcv", "fcmp s3, s2", "csel w4, w20, w21, gt", @@ -2809,7 +2809,7 @@ "frinti s2, s16", "fcvtzs x20, s2", "mov x21, #0x8000000000000000", - "ldr s3, [x28, #2816]", + "ldr s3, [x28, #2848]", "mrs x22, nzcv", "fcmp s3, s2", "csel x4, x20, x21, gt", @@ -2825,7 +2825,7 @@ "frinti d2, d16", "fcvtzs x20, d2", "mov x21, #0x8000000000000000", - "ldr d3, [x28, #2864]", + "ldr d3, [x28, #2896]", "mrs x22, nzcv", "fcmp d3, d2", "csel x4, x20, x21, gt", @@ -2841,7 +2841,7 @@ "frinti d2, d16", "fcvtzs x20, d2", "mov x21, #0x8000000000000000", - "ldr d3, [x28, #2864]", + "ldr d3, [x28, #2896]", "mrs x22, nzcv", "fcmp d3, d2", "csel x4, x20, x21, gt", @@ -3153,8 +3153,8 @@ ], "ExpectedArm64ASM": [ "frinti v2.4s, v17.4s", - "ldr q3, [x28, #2880]", - "ldr q4, [x28, #2784]", + "ldr q3, [x28, #2912]", + "ldr q4, [x28, #2816]", "fcvtzs v5.4s, v2.4s", "fcmgt v2.4s, v4.4s, v2.4s", "mov v16.16b, v2.16b", @@ -3171,8 +3171,8 @@ "ExpectedArm64ASM": [ "ldr q2, [x28, #32]", "frinti v3.4s, v17.4s", - "ldr q4, [x28, #2880]", - "ldr q5, [x28, #2784]", + "ldr q4, [x28, #2912]", + "ldr q5, [x28, #2816]", "fcvtzs v6.4s, v3.4s", "fcmgt v3.4s, v5.4s, v3.4s", "mov v16.16b, v3.16b", @@ -3190,8 +3190,8 @@ "Map 1 0b10 0x5b 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2880]", - "ldr q3, [x28, #2784]", + "ldr q2, [x28, #2912]", + "ldr q3, [x28, #2816]", "fcvtzs v4.4s, v17.4s", "fcmgt v3.4s, v3.4s, v17.4s", "mov v16.16b, v3.16b", @@ -3207,8 +3207,8 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x28, #32]", - "ldr q3, [x28, #2880]", - "ldr q4, [x28, #2784]", + "ldr q3, [x28, #2912]", + "ldr q4, [x28, #2816]", "fcvtzs v5.4s, v17.4s", "fcmgt v6.4s, v4.4s, v17.4s", "mov v16.16b, v6.16b", @@ -3984,7 +3984,7 @@ "Map 1 0b01 0xd0 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2432]", + "ldr q2, [x28, #2464]", "eor v2.16b, v18.16b, v2.16b", "fadd v16.2d, v17.2d, v2.2d", "movi v2.2d, #0x0", @@ -3999,7 +3999,7 @@ "ExpectedArm64ASM": [ "ldr q2, [x28, #32]", "ldr q3, [x28, #48]", - "ldr q4, [x28, #2432]", + "ldr q4, [x28, #2464]", "eor v5.16b, v18.16b, v4.16b", "fadd v16.2d, v17.2d, v5.2d", "eor v3.16b, v3.16b, v4.16b", @@ -4013,7 +4013,7 @@ "Map 1 0b11 0xd0 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2400]", + "ldr q2, [x28, #2432]", "eor v2.16b, v18.16b, v2.16b", "fadd v16.4s, v17.4s, v2.4s", "movi v2.2d, #0x0", @@ -4028,7 +4028,7 @@ "ExpectedArm64ASM": [ "ldr q2, [x28, #32]", "ldr q3, [x28, #48]", - "ldr q4, [x28, #2400]", + "ldr q4, [x28, #2432]", "eor v5.16b, v18.16b, v4.16b", "fadd v16.4s, v17.4s, v5.4s", "eor v3.16b, v3.16b, v4.16b", @@ -4204,7 +4204,7 @@ "Map 1 0b01 0xd7 256-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2656]", + "ldr q2, [x28, #2688]", "cmlt v3.16b, v16.16b, #0", "and v2.16b, v3.16b, v2.16b", "addp v2.16b, v2.16b, v2.16b", @@ -4220,7 +4220,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x28, #16]", - "ldr q3, [x28, #2656]", + "ldr q3, [x28, #2688]", "cmlt v4.16b, v16.16b, #0", "and v4.16b, v4.16b, v3.16b", "addp v4.16b, v4.16b, v4.16b", @@ -4726,8 +4726,8 @@ "Map 1 0b01 0xe6 128-bit" ], "ExpectedArm64ASM": [ - "ldr d2, [x28, #2880]", - "ldr q3, [x28, #2832]", + "ldr d2, [x28, #2912]", + "ldr q3, [x28, #2864]", "frintz v4.2d, v17.2d", "fcvtn v4.2s, v4.2d", "fcvtzs v4.2s, v4.2s", @@ -4746,8 +4746,8 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x28, #32]", - "ldr q3, [x28, #2880]", - "ldr q4, [x28, #2832]", + "ldr q3, [x28, #2912]", + "ldr q4, [x28, #2864]", "frintz v5.2d, v17.2d", "fcvtn v5.2s, v5.2d", "fcvtzs v5.2s, v5.2s", @@ -4797,8 +4797,8 @@ ], "ExpectedArm64ASM": [ "frinti v2.2d, v17.2d", - "ldr d3, [x28, #2880]", - "ldr q4, [x28, #2832]", + "ldr d3, [x28, #2912]", + "ldr q4, [x28, #2864]", "frintz v5.2d, v2.2d", "fcvtn v5.2s, v5.2d", "fcvtzs v5.2s, v5.2s", @@ -4818,8 +4818,8 @@ "ExpectedArm64ASM": [ "ldr q2, [x28, #32]", "frinti v3.2d, v17.2d", - "ldr q4, [x28, #2880]", - "ldr q5, [x28, #2832]", + "ldr q4, [x28, #2912]", + "ldr q5, [x28, #2864]", "frintz v6.2d, v3.2d", "fcvtn v6.2s, v6.2d", "fcvtzs v6.2s, v6.2s", diff --git a/unittests/InstructionCountCI/AVX128/VEX_map2.json b/unittests/InstructionCountCI/AVX128/VEX_map2.json index ba07008447..52650dd084 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map2.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map2.json @@ -1964,7 +1964,7 @@ "Map 2 0b01 0x41 256-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2368]", + "ldr q2, [x28, #2400]", "zip1 v3.8h, v2.8h, v17.8h", "zip2 v2.8h, v2.8h, v17.8h", "umin v2.4s, v3.4s, v2.4s", @@ -4548,7 +4548,7 @@ "Map 2 0b01 0x96 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2400]", + "ldr q2, [x28, #2432]", "eor v2.16b, v17.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.4s, v16.4s, v18.4s", @@ -4566,7 +4566,7 @@ "ldr q2, [x28, #16]", "ldr q3, [x28, #32]", "ldr q4, [x28, #48]", - "ldr q5, [x28, #2400]", + "ldr q5, [x28, #2432]", "eor v6.16b, v17.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.4s, v16.4s, v18.4s", @@ -4582,7 +4582,7 @@ "Map 2 0b01 0x96 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2432]", + "ldr q2, [x28, #2464]", "eor v2.16b, v17.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.2d, v16.2d, v18.2d", @@ -4600,7 +4600,7 @@ "ldr q2, [x28, #16]", "ldr q3, [x28, #32]", "ldr q4, [x28, #48]", - "ldr q5, [x28, #2432]", + "ldr q5, [x28, #2464]", "eor v6.16b, v17.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.2d, v16.2d, v18.2d", @@ -4616,7 +4616,7 @@ "Map 2 0b01 0x97 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2464]", + "ldr q2, [x28, #2496]", "eor v2.16b, v17.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.4s, v16.4s, v18.4s", @@ -4634,7 +4634,7 @@ "ldr q2, [x28, #16]", "ldr q3, [x28, #32]", "ldr q4, [x28, #48]", - "ldr q5, [x28, #2464]", + "ldr q5, [x28, #2496]", "eor v6.16b, v17.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.4s, v16.4s, v18.4s", @@ -4650,7 +4650,7 @@ "Map 2 0b01 0x97 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2496]", + "ldr q2, [x28, #2528]", "eor v2.16b, v17.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.2d, v16.2d, v18.2d", @@ -4668,7 +4668,7 @@ "ldr q2, [x28, #16]", "ldr q3, [x28, #32]", "ldr q4, [x28, #48]", - "ldr q5, [x28, #2496]", + "ldr q5, [x28, #2528]", "eor v6.16b, v17.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.2d, v16.2d, v18.2d", @@ -5656,7 +5656,7 @@ "Map 2 0b01 0xa6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2400]", + "ldr q2, [x28, #2432]", "eor v2.16b, v18.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.4s, v17.4s, v16.4s", @@ -5674,7 +5674,7 @@ "ldr q2, [x28, #16]", "ldr q3, [x28, #32]", "ldr q4, [x28, #48]", - "ldr q5, [x28, #2400]", + "ldr q5, [x28, #2432]", "eor v6.16b, v18.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.4s, v17.4s, v16.4s", @@ -5690,7 +5690,7 @@ "Map 2 0b01 0xa6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2432]", + "ldr q2, [x28, #2464]", "eor v2.16b, v18.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.2d, v17.2d, v16.2d", @@ -5708,7 +5708,7 @@ "ldr q2, [x28, #16]", "ldr q3, [x28, #32]", "ldr q4, [x28, #48]", - "ldr q5, [x28, #2432]", + "ldr q5, [x28, #2464]", "eor v6.16b, v18.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.2d, v17.2d, v16.2d", @@ -5724,7 +5724,7 @@ "Map 2 0b01 0xa7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2464]", + "ldr q2, [x28, #2496]", "eor v2.16b, v18.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.4s, v17.4s, v16.4s", @@ -5742,7 +5742,7 @@ "ldr q2, [x28, #16]", "ldr q3, [x28, #32]", "ldr q4, [x28, #48]", - "ldr q5, [x28, #2464]", + "ldr q5, [x28, #2496]", "eor v6.16b, v18.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.4s, v17.4s, v16.4s", @@ -5758,7 +5758,7 @@ "Map 2 0b01 0xa7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2496]", + "ldr q2, [x28, #2528]", "eor v2.16b, v18.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.2d, v17.2d, v16.2d", @@ -5776,7 +5776,7 @@ "ldr q2, [x28, #16]", "ldr q3, [x28, #32]", "ldr q4, [x28, #48]", - "ldr q5, [x28, #2496]", + "ldr q5, [x28, #2528]", "eor v6.16b, v18.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.2d, v17.2d, v16.2d", @@ -5792,7 +5792,7 @@ "Map 2 0b01 0xb6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2400]", + "ldr q2, [x28, #2432]", "eor v2.16b, v16.16b, v2.16b", "mov v16.16b, v2.16b", "fmla v16.4s, v17.4s, v18.4s", @@ -5809,7 +5809,7 @@ "ldr q2, [x28, #16]", "ldr q3, [x28, #32]", "ldr q4, [x28, #48]", - "ldr q5, [x28, #2400]", + "ldr q5, [x28, #2432]", "eor v6.16b, v16.16b, v5.16b", "mov v16.16b, v6.16b", "fmla v16.4s, v17.4s, v18.4s", @@ -5824,7 +5824,7 @@ "Map 2 0b01 0xb6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2432]", + "ldr q2, [x28, #2464]", "eor v2.16b, v16.16b, v2.16b", "mov v16.16b, v2.16b", "fmla v16.2d, v17.2d, v18.2d", @@ -5841,7 +5841,7 @@ "ldr q2, [x28, #16]", "ldr q3, [x28, #32]", "ldr q4, [x28, #48]", - "ldr q5, [x28, #2432]", + "ldr q5, [x28, #2464]", "eor v6.16b, v16.16b, v5.16b", "mov v16.16b, v6.16b", "fmla v16.2d, v17.2d, v18.2d", @@ -5856,7 +5856,7 @@ "Map 2 0b01 0xb7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2464]", + "ldr q2, [x28, #2496]", "eor v2.16b, v16.16b, v2.16b", "mov v16.16b, v2.16b", "fmla v16.4s, v17.4s, v18.4s", @@ -5873,7 +5873,7 @@ "ldr q2, [x28, #16]", "ldr q3, [x28, #32]", "ldr q4, [x28, #48]", - "ldr q5, [x28, #2464]", + "ldr q5, [x28, #2496]", "eor v6.16b, v16.16b, v5.16b", "mov v16.16b, v6.16b", "fmla v16.4s, v17.4s, v18.4s", @@ -5888,7 +5888,7 @@ "Map 2 0b01 0xb7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2496]", + "ldr q2, [x28, #2528]", "eor v2.16b, v16.16b, v2.16b", "mov v16.16b, v2.16b", "fmla v16.2d, v17.2d, v18.2d", @@ -5905,7 +5905,7 @@ "ldr q2, [x28, #16]", "ldr q3, [x28, #32]", "ldr q4, [x28, #48]", - "ldr q5, [x28, #2496]", + "ldr q5, [x28, #2528]", "eor v6.16b, v16.16b, v5.16b", "mov v16.16b, v6.16b", "fmla v16.2d, v17.2d, v18.2d", diff --git a/unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json b/unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json index 4cc0f954d0..f0dd656a5f 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json @@ -2850,7 +2850,7 @@ "Map 2 0b01 0x96 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2400]", + "ldr q2, [x28, #2432]", "eor v2.16b, v17.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.4s, v16.4s, v18.4s", @@ -2868,7 +2868,7 @@ "ldr q2, [x28, #16]", "ldr q3, [x28, #32]", "ldr q4, [x28, #48]", - "ldr q5, [x28, #2400]", + "ldr q5, [x28, #2432]", "eor v6.16b, v17.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.4s, v16.4s, v18.4s", @@ -2884,7 +2884,7 @@ "Map 2 0b01 0x96 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2432]", + "ldr q2, [x28, #2464]", "eor v2.16b, v17.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.2d, v16.2d, v18.2d", @@ -2902,7 +2902,7 @@ "ldr q2, [x28, #16]", "ldr q3, [x28, #32]", "ldr q4, [x28, #48]", - "ldr q5, [x28, #2432]", + "ldr q5, [x28, #2464]", "eor v6.16b, v17.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.2d, v16.2d, v18.2d", @@ -2918,7 +2918,7 @@ "Map 2 0b01 0x97 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2464]", + "ldr q2, [x28, #2496]", "eor v2.16b, v17.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.4s, v16.4s, v18.4s", @@ -2936,7 +2936,7 @@ "ldr q2, [x28, #16]", "ldr q3, [x28, #32]", "ldr q4, [x28, #48]", - "ldr q5, [x28, #2464]", + "ldr q5, [x28, #2496]", "eor v6.16b, v17.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.4s, v16.4s, v18.4s", @@ -2952,7 +2952,7 @@ "Map 2 0b01 0x97 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2496]", + "ldr q2, [x28, #2528]", "eor v2.16b, v17.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.2d, v16.2d, v18.2d", @@ -2970,7 +2970,7 @@ "ldr q2, [x28, #16]", "ldr q3, [x28, #32]", "ldr q4, [x28, #48]", - "ldr q5, [x28, #2496]", + "ldr q5, [x28, #2528]", "eor v6.16b, v17.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.2d, v16.2d, v18.2d", @@ -3938,7 +3938,7 @@ "Map 2 0b01 0xa6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2400]", + "ldr q2, [x28, #2432]", "eor v2.16b, v18.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.4s, v17.4s, v16.4s", @@ -3956,7 +3956,7 @@ "ldr q2, [x28, #16]", "ldr q3, [x28, #32]", "ldr q4, [x28, #48]", - "ldr q5, [x28, #2400]", + "ldr q5, [x28, #2432]", "eor v6.16b, v18.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.4s, v17.4s, v16.4s", @@ -3972,7 +3972,7 @@ "Map 2 0b01 0xa6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2432]", + "ldr q2, [x28, #2464]", "eor v2.16b, v18.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.2d, v17.2d, v16.2d", @@ -3990,7 +3990,7 @@ "ldr q2, [x28, #16]", "ldr q3, [x28, #32]", "ldr q4, [x28, #48]", - "ldr q5, [x28, #2432]", + "ldr q5, [x28, #2464]", "eor v6.16b, v18.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.2d, v17.2d, v16.2d", @@ -4006,7 +4006,7 @@ "Map 2 0b01 0xa7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2464]", + "ldr q2, [x28, #2496]", "eor v2.16b, v18.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.4s, v17.4s, v16.4s", @@ -4024,7 +4024,7 @@ "ldr q2, [x28, #16]", "ldr q3, [x28, #32]", "ldr q4, [x28, #48]", - "ldr q5, [x28, #2464]", + "ldr q5, [x28, #2496]", "eor v6.16b, v18.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.4s, v17.4s, v16.4s", @@ -4040,7 +4040,7 @@ "Map 2 0b01 0xa7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2496]", + "ldr q2, [x28, #2528]", "eor v2.16b, v18.16b, v2.16b", "mov v0.16b, v2.16b", "fmla v0.2d, v17.2d, v16.2d", @@ -4058,7 +4058,7 @@ "ldr q2, [x28, #16]", "ldr q3, [x28, #32]", "ldr q4, [x28, #48]", - "ldr q5, [x28, #2496]", + "ldr q5, [x28, #2528]", "eor v6.16b, v18.16b, v5.16b", "mov v0.16b, v6.16b", "fmla v0.2d, v17.2d, v16.2d", @@ -4074,7 +4074,7 @@ "Map 2 0b01 0xb6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2400]", + "ldr q2, [x28, #2432]", "eor v2.16b, v16.16b, v2.16b", "mov v16.16b, v2.16b", "fmla v16.4s, v17.4s, v18.4s", @@ -4091,7 +4091,7 @@ "ldr q2, [x28, #16]", "ldr q3, [x28, #32]", "ldr q4, [x28, #48]", - "ldr q5, [x28, #2400]", + "ldr q5, [x28, #2432]", "eor v6.16b, v16.16b, v5.16b", "mov v16.16b, v6.16b", "fmla v16.4s, v17.4s, v18.4s", @@ -4106,7 +4106,7 @@ "Map 2 0b01 0xb6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2432]", + "ldr q2, [x28, #2464]", "eor v2.16b, v16.16b, v2.16b", "mov v16.16b, v2.16b", "fmla v16.2d, v17.2d, v18.2d", @@ -4123,7 +4123,7 @@ "ldr q2, [x28, #16]", "ldr q3, [x28, #32]", "ldr q4, [x28, #48]", - "ldr q5, [x28, #2432]", + "ldr q5, [x28, #2464]", "eor v6.16b, v16.16b, v5.16b", "mov v16.16b, v6.16b", "fmla v16.2d, v17.2d, v18.2d", @@ -4138,7 +4138,7 @@ "Map 2 0b01 0xb7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2464]", + "ldr q2, [x28, #2496]", "eor v2.16b, v16.16b, v2.16b", "mov v16.16b, v2.16b", "fmla v16.4s, v17.4s, v18.4s", @@ -4155,7 +4155,7 @@ "ldr q2, [x28, #16]", "ldr q3, [x28, #32]", "ldr q4, [x28, #48]", - "ldr q5, [x28, #2464]", + "ldr q5, [x28, #2496]", "eor v6.16b, v16.16b, v5.16b", "mov v16.16b, v6.16b", "fmla v16.4s, v17.4s, v18.4s", @@ -4170,7 +4170,7 @@ "Map 2 0b01 0xb7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2496]", + "ldr q2, [x28, #2528]", "eor v2.16b, v16.16b, v2.16b", "mov v16.16b, v2.16b", "fmla v16.2d, v17.2d, v18.2d", @@ -4187,7 +4187,7 @@ "ldr q2, [x28, #16]", "ldr q3, [x28, #32]", "ldr q4, [x28, #48]", - "ldr q5, [x28, #2496]", + "ldr q5, [x28, #2528]", "eor v6.16b, v16.16b, v5.16b", "mov v16.16b, v6.16b", "fmla v16.2d, v17.2d, v18.2d", diff --git a/unittests/InstructionCountCI/AVX128/VEX_map3.json b/unittests/InstructionCountCI/AVX128/VEX_map3.json index e596c6639e..3bba870d4a 100644 --- a/unittests/InstructionCountCI/AVX128/VEX_map3.json +++ b/unittests/InstructionCountCI/AVX128/VEX_map3.json @@ -343,7 +343,7 @@ "Map 3 0b01 0x02 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2560]", + "ldr q2, [x28, #2592]", "tbx v16.16b, {v17.16b}, v2.16b", "movi v2.2d, #0x0", "str q2, [x28, #16]" @@ -355,7 +355,7 @@ "Map 3 0b01 0x02 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2576]", + "ldr q2, [x28, #2608]", "tbx v16.16b, {v17.16b}, v2.16b", "movi v2.2d, #0x0", "str q2, [x28, #16]" @@ -378,7 +378,7 @@ "Map 3 0b01 0x02 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2592]", + "ldr q2, [x28, #2624]", "tbx v16.16b, {v17.16b}, v2.16b", "movi v2.2d, #0x0", "str q2, [x28, #16]" @@ -402,7 +402,7 @@ "Map 3 0b01 0x02 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2608]", + "ldr q2, [x28, #2640]", "tbx v16.16b, {v17.16b}, v2.16b", "movi v2.2d, #0x0", "str q2, [x28, #16]" @@ -425,7 +425,7 @@ "Map 3 0b01 0x02 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2624]", + "ldr q2, [x28, #2656]", "tbx v16.16b, {v17.16b}, v2.16b", "movi v2.2d, #0x0", "str q2, [x28, #16]" @@ -437,7 +437,7 @@ "Map 3 0b01 0x02 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2640]", + "ldr q2, [x28, #2672]", "tbx v16.16b, {v17.16b}, v2.16b", "movi v2.2d, #0x0", "str q2, [x28, #16]" @@ -3576,7 +3576,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2304]", + "ldr x0, [x28, #2336]", "br x0" ] }, @@ -3591,7 +3591,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2304]", + "ldr x0, [x28, #2336]", "br x0" ] }, @@ -3606,7 +3606,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2304]", + "ldr x0, [x28, #2336]", "br x0" ] }, @@ -3621,7 +3621,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2304]", + "ldr x0, [x28, #2336]", "br x0" ] }, @@ -3636,7 +3636,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2304]", + "ldr x0, [x28, #2336]", "br x0" ] }, @@ -3651,7 +3651,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2304]", + "ldr x0, [x28, #2336]", "br x0" ] }, @@ -3666,7 +3666,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2304]", + "ldr x0, [x28, #2336]", "br x0" ] }, @@ -3681,7 +3681,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2304]", + "ldr x0, [x28, #2336]", "br x0" ] }, @@ -3696,7 +3696,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2304]", + "ldr x0, [x28, #2336]", "br x0" ] }, @@ -3711,7 +3711,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2304]", + "ldr x0, [x28, #2336]", "br x0" ] }, @@ -3726,7 +3726,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2304]", + "ldr x0, [x28, #2336]", "br x0" ] }, @@ -3741,7 +3741,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2304]", + "ldr x0, [x28, #2336]", "br x0" ] }, @@ -3756,7 +3756,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2304]", + "ldr x0, [x28, #2336]", "br x0" ] }, @@ -3771,7 +3771,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2304]", + "ldr x0, [x28, #2336]", "br x0" ] }, @@ -3786,7 +3786,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2304]", + "ldr x0, [x28, #2336]", "br x0" ] }, @@ -3801,7 +3801,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2304]", + "ldr x0, [x28, #2336]", "br x0" ] }, @@ -3816,7 +3816,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2304]", + "ldr x0, [x28, #2336]", "br x0" ] }, @@ -3831,7 +3831,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2304]", + "ldr x0, [x28, #2336]", "br x0" ] }, @@ -3846,7 +3846,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2304]", + "ldr x0, [x28, #2336]", "br x0" ] }, @@ -3861,7 +3861,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2304]", + "ldr x0, [x28, #2336]", "br x0" ] }, @@ -3876,7 +3876,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2304]", + "ldr x0, [x28, #2336]", "br x0" ] }, @@ -3891,7 +3891,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2304]", + "ldr x0, [x28, #2336]", "br x0" ] }, @@ -3906,7 +3906,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2304]", + "ldr x0, [x28, #2336]", "br x0" ] }, @@ -3921,7 +3921,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2304]", + "ldr x0, [x28, #2336]", "br x0" ] }, @@ -3936,7 +3936,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2304]", + "ldr x0, [x28, #2336]", "br x0" ] }, @@ -3951,7 +3951,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2304]", + "ldr x0, [x28, #2336]", "br x0" ] }, @@ -3966,7 +3966,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2304]", + "ldr x0, [x28, #2336]", "br x0" ] }, @@ -3981,7 +3981,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2304]", + "ldr x0, [x28, #2336]", "br x0" ] }, @@ -3996,7 +3996,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2304]", + "ldr x0, [x28, #2336]", "br x0" ] }, @@ -4011,7 +4011,7 @@ "str x20, [x28, #272]", "mov w1, #0x401", "str x1, [x28, #1328]", - "ldr x0, [x28, #2304]", + "ldr x0, [x28, #2336]", "br x0" ] }, @@ -4022,7 +4022,7 @@ ], "ExpectedArm64ASM": [ "movi v2.2d, #0x0", - "ldr q3, [x28, #2544]", + "ldr q3, [x28, #2576]", "mov v16.16b, v17.16b", "unimplemented (Unimplemented)", "tbl v16.16b, {v16.16b}, v3.16b", @@ -4036,7 +4036,7 @@ ], "ExpectedArm64ASM": [ "movi v2.2d, #0x0", - "ldr q3, [x28, #2544]", + "ldr q3, [x28, #2576]", "mov v16.16b, v17.16b", "unimplemented (Unimplemented)", "tbl v16.16b, {v16.16b}, v3.16b", diff --git a/unittests/InstructionCountCI/Crypto/H0F3A.json b/unittests/InstructionCountCI/Crypto/H0F3A.json index 81e4a81b81..f0d3aad456 100644 --- a/unittests/InstructionCountCI/Crypto/H0F3A.json +++ b/unittests/InstructionCountCI/Crypto/H0F3A.json @@ -55,7 +55,7 @@ "0x66 0x0f 0x3a 0xdf" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2544]", + "ldr q2, [x28, #2576]", "movi v3.2d, #0x0", "mov v16.16b, v17.16b", "unimplemented (Unimplemented)", @@ -68,7 +68,7 @@ "0x66 0x0f 0x3a 0xdf" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2544]", + "ldr q2, [x28, #2576]", "movi v3.2d, #0x0", "mov v16.16b, v17.16b", "unimplemented (Unimplemented)", @@ -79,235 +79,75 @@ ] }, "sha1rnds4 xmm0, xmm1, 00b": { - "ExpectedInstructionCount": 51, + "ExpectedInstructionCount": 10, "Comment": [ "0x66 0x0f 0x3a 0xcc" ], "ExpectedArm64ASM": [ - "mov w20, #0x7999", - "movk w20, #0x5a82, lsl #16", - "mov w21, v17.s[3]", - "mov w22, v16.s[3]", - "mov w23, v16.s[2]", - "mov w24, v16.s[1]", - "mov w25, v16.s[0]", - "and w30, w23, w24", - "bic w18, w25, w23", - "eor w30, w30, w18", - "ror w18, w22, #27", - "add w30, w30, w18", - "add w21, w30, w21", - "add w21, w21, w20", - "ror w23, w23, #2", - "mov w30, v17.s[2]", - "add w25, w30, w25", - "and w30, w22, w23", - "bic w18, w24, w22", - "eor w30, w30, w18", - "ror w18, w21, #27", - "add w30, w30, w18", - "add w25, w30, w25", - "add w25, w25, w20", - "ror w22, w22, #2", - "mov w30, v17.s[1]", - "add w24, w30, w24", - "and w30, w21, w22", - "bic w18, w23, w21", - "eor w30, w30, w18", - "ror w18, w25, #27", - "add w30, w30, w18", - "add w24, w30, w24", - "add w24, w24, w20", - "ror w21, w21, #2", - "mov w30, v17.s[0]", - "add w23, w30, w23", - "and w30, w25, w21", - "bic w22, w22, w25", - "eor w22, w30, w22", - "ror w30, w24, #27", - "add w22, w22, w30", - "add w22, w22, w23", - "add w20, w22, w20", - "ror w22, w25, #2", - "mov v2.16b, v16.16b", - "mov v2.s[3], w20", - "mov v2.s[2], w24", - "mov v2.s[1], w22", - "mov v16.16b, v2.16b", - "mov v16.s[0], w21" + "ldr q2, [x28, #2960]", + "movi v3.2d, #0x0", + "rev64 v4.4s, v16.4s", + "ext v4.16b, v4.16b, v4.16b, #8", + "rev64 v5.4s, v17.4s", + "ext v5.16b, v5.16b, v5.16b, #8", + "add v2.4s, v5.4s, v2.4s", + "unimplemented (Unimplemented)", + "rev64 v2.4s, v4.4s", + "ext v16.16b, v2.16b, v2.16b, #8" ] }, "sha1rnds4 xmm0, xmm1, 01b": { - "ExpectedInstructionCount": 47, + "ExpectedInstructionCount": 10, "Comment": [ "0x66 0x0f 0x3a 0xcc" ], "ExpectedArm64ASM": [ - "mov w20, #0xeba1", - "movk w20, #0x6ed9, lsl #16", - "mov w21, v17.s[3]", - "mov w22, v16.s[3]", - "mov w23, v16.s[2]", - "mov w24, v16.s[1]", - "mov w25, v16.s[0]", - "eor w30, w23, w24", - "eor w30, w30, w25", - "ror w18, w22, #27", - "add w30, w30, w18", - "add w21, w30, w21", - "add w21, w21, w20", - "ror w23, w23, #2", - "mov w30, v17.s[2]", - "add w25, w30, w25", - "eor w30, w22, w23", - "eor w30, w30, w24", - "ror w18, w21, #27", - "add w30, w30, w18", - "add w25, w30, w25", - "add w25, w25, w20", - "ror w22, w22, #2", - "mov w30, v17.s[1]", - "add w24, w30, w24", - "eor w30, w21, w22", - "eor w30, w30, w23", - "ror w18, w25, #27", - "add w30, w30, w18", - "add w24, w30, w24", - "add w24, w24, w20", - "ror w21, w21, #2", - "mov w30, v17.s[0]", - "add w23, w30, w23", - "eor w30, w25, w21", - "eor w22, w30, w22", - "ror w30, w24, #27", - "add w22, w22, w30", - "add w22, w22, w23", - "add w20, w22, w20", - "ror w22, w25, #2", - "mov v2.16b, v16.16b", - "mov v2.s[3], w20", - "mov v2.s[2], w24", - "mov v2.s[1], w22", - "mov v16.16b, v2.16b", - "mov v16.s[0], w21" + "ldr q2, [x28, #2976]", + "movi v3.2d, #0x0", + "rev64 v4.4s, v16.4s", + "ext v4.16b, v4.16b, v4.16b, #8", + "rev64 v5.4s, v17.4s", + "ext v5.16b, v5.16b, v5.16b, #8", + "add v2.4s, v5.4s, v2.4s", + "unimplemented (Unimplemented)", + "rev64 v2.4s, v4.4s", + "ext v16.16b, v2.16b, v2.16b, #8" ] }, "sha1rnds4 xmm0, xmm1, 10b": { - "ExpectedInstructionCount": 55, + "ExpectedInstructionCount": 10, "Comment": [ "0x66 0x0f 0x3a 0xcc" ], "ExpectedArm64ASM": [ - "mov w20, #0xbcdc", - "movk w20, #0x8f1b, lsl #16", - "mov w21, v17.s[3]", - "mov w22, v16.s[3]", - "mov w23, v16.s[2]", - "mov w24, v16.s[1]", - "mov w25, v16.s[0]", - "and w30, w24, w25", - "orr w18, w24, w25", - "and w18, w23, w18", - "orr w30, w18, w30", - "ror w18, w22, #27", - "add w30, w30, w18", - "add w21, w30, w21", - "add w21, w21, w20", - "ror w23, w23, #2", - "mov w30, v17.s[2]", - "add w25, w30, w25", - "and w30, w23, w24", - "orr w18, w23, w24", - "and w18, w22, w18", - "orr w30, w18, w30", - "ror w18, w21, #27", - "add w30, w30, w18", - "add w25, w30, w25", - "add w25, w25, w20", - "ror w22, w22, #2", - "mov w30, v17.s[1]", - "add w24, w30, w24", - "and w30, w22, w23", - "orr w18, w22, w23", - "and w18, w21, w18", - "orr w30, w18, w30", - "ror w18, w25, #27", - "add w30, w30, w18", - "add w24, w30, w24", - "add w24, w24, w20", - "ror w21, w21, #2", - "mov w30, v17.s[0]", - "add w23, w30, w23", - "and w30, w21, w22", - "orr w22, w21, w22", - "and w22, w25, w22", - "orr w22, w22, w30", - "ror w30, w24, #27", - "add w22, w22, w30", - "add w22, w22, w23", - "add w20, w22, w20", - "ror w22, w25, #2", - "mov v2.16b, v16.16b", - "mov v2.s[3], w20", - "mov v2.s[2], w24", - "mov v2.s[1], w22", - "mov v16.16b, v2.16b", - "mov v16.s[0], w21" + "ldr q2, [x28, #2992]", + "movi v3.2d, #0x0", + "rev64 v4.4s, v16.4s", + "ext v4.16b, v4.16b, v4.16b, #8", + "rev64 v5.4s, v17.4s", + "ext v5.16b, v5.16b, v5.16b, #8", + "add v2.4s, v5.4s, v2.4s", + "unimplemented (Unimplemented)", + "rev64 v2.4s, v4.4s", + "ext v16.16b, v2.16b, v2.16b, #8" ] }, "sha1rnds4 xmm0, xmm1, 11b": { - "ExpectedInstructionCount": 47, + "ExpectedInstructionCount": 10, "Comment": [ "0x66 0x0f 0x3a 0xcc" ], "ExpectedArm64ASM": [ - "mov w20, #0xc1d6", - "movk w20, #0xca62, lsl #16", - "mov w21, v17.s[3]", - "mov w22, v16.s[3]", - "mov w23, v16.s[2]", - "mov w24, v16.s[1]", - "mov w25, v16.s[0]", - "eor w30, w23, w24", - "eor w30, w30, w25", - "ror w18, w22, #27", - "add w30, w30, w18", - "add w21, w30, w21", - "add w21, w21, w20", - "ror w23, w23, #2", - "mov w30, v17.s[2]", - "add w25, w30, w25", - "eor w30, w22, w23", - "eor w30, w30, w24", - "ror w18, w21, #27", - "add w30, w30, w18", - "add w25, w30, w25", - "add w25, w25, w20", - "ror w22, w22, #2", - "mov w30, v17.s[1]", - "add w24, w30, w24", - "eor w30, w21, w22", - "eor w30, w30, w23", - "ror w18, w25, #27", - "add w30, w30, w18", - "add w24, w30, w24", - "add w24, w24, w20", - "ror w21, w21, #2", - "mov w30, v17.s[0]", - "add w23, w30, w23", - "eor w30, w25, w21", - "eor w22, w30, w22", - "ror w30, w24, #27", - "add w22, w22, w30", - "add w22, w22, w23", - "add w20, w22, w20", - "ror w22, w25, #2", - "mov v2.16b, v16.16b", - "mov v2.s[3], w20", - "mov v2.s[2], w24", - "mov v2.s[1], w22", - "mov v16.16b, v2.16b", - "mov v16.s[0], w21" + "ldr q2, [x28, #3008]", + "movi v3.2d, #0x0", + "rev64 v4.4s, v16.4s", + "ext v4.16b, v4.16b, v4.16b, #8", + "rev64 v5.4s, v17.4s", + "ext v5.16b, v5.16b, v5.16b, #8", + "add v2.4s, v5.4s, v2.4s", + "unimplemented (Unimplemented)", + "rev64 v2.4s, v4.4s", + "ext v16.16b, v2.16b, v2.16b, #8" ] } } diff --git a/unittests/InstructionCountCI/DDD.json b/unittests/InstructionCountCI/DDD.json index 7d8d17f617..fb2391a6bb 100644 --- a/unittests/InstructionCountCI/DDD.json +++ b/unittests/InstructionCountCI/DDD.json @@ -65,8 +65,8 @@ ], "ExpectedArm64ASM": [ "ldr d2, [x28, #1056]", - "ldr d3, [x28, #2880]", - "ldr d4, [x28, #2784]", + "ldr d3, [x28, #2912]", + "ldr d4, [x28, #2816]", "fcvtzs v5.2s, v2.2s", "fcmgt v2.4s, v4.4s, v2.4s", "bsl v2.8b, v5.8b, v3.8b", diff --git a/unittests/InstructionCountCI/FlagM/Secondary.json b/unittests/InstructionCountCI/FlagM/Secondary.json index 10b3028a8a..2f33bae555 100644 --- a/unittests/InstructionCountCI/FlagM/Secondary.json +++ b/unittests/InstructionCountCI/FlagM/Secondary.json @@ -1608,7 +1608,7 @@ "Comment": "0x0f 0xd7", "ExpectedArm64ASM": [ "ldr d2, [x28, #1040]", - "ldr d3, [x28, #2656]", + "ldr d3, [x28, #2688]", "cmlt v2.16b, v2.16b, #0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v2.16b", diff --git a/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json b/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json index 0d8a872b1d..24f45e81ba 100644 --- a/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json +++ b/unittests/InstructionCountCI/FlagM/Secondary_OpSize.json @@ -37,7 +37,7 @@ "ExpectedInstructionCount": 7, "Comment": "0x66 0x0f 0xd7", "ExpectedArm64ASM": [ - "ldr q2, [x28, #2656]", + "ldr q2, [x28, #2688]", "cmlt v3.16b, v16.16b, #0", "and v2.16b, v3.16b, v2.16b", "addp v2.16b, v2.16b, v2.16b", diff --git a/unittests/InstructionCountCI/FlagM/VEX_map1.json b/unittests/InstructionCountCI/FlagM/VEX_map1.json index d352e22a4a..7d967b3083 100644 --- a/unittests/InstructionCountCI/FlagM/VEX_map1.json +++ b/unittests/InstructionCountCI/FlagM/VEX_map1.json @@ -68,7 +68,7 @@ "Map 1 0b01 0xd7 256-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2656]", + "ldr q2, [x28, #2688]", "cmlt v3.16b, v16.16b, #0", "and v2.16b, v3.16b, v2.16b", "addp v2.16b, v2.16b, v2.16b", diff --git a/unittests/InstructionCountCI/FlagM/x87-Crysis2Max-fmodel.json b/unittests/InstructionCountCI/FlagM/x87-Crysis2Max-fmodel.json index e8701c673d..ba1d061c66 100644 --- a/unittests/InstructionCountCI/FlagM/x87-Crysis2Max-fmodel.json +++ b/unittests/InstructionCountCI/FlagM/x87-Crysis2Max-fmodel.json @@ -26854,7 +26854,7 @@ "lsl w21, w23, w21", "bic w21, w22, w21", "strb w21, [x28, #1298]", - "ldr x0, [x28, #2344]", + "ldr x0, [x28, #2376]", "ubfiz x3, x20, #4, #20", "add x0, x0, x3", "ldp x1, x0, [x0]" diff --git a/unittests/InstructionCountCI/FlagM/x87-HalfLife.json b/unittests/InstructionCountCI/FlagM/x87-HalfLife.json index 6b11c78a9d..f265e096b1 100644 --- a/unittests/InstructionCountCI/FlagM/x87-HalfLife.json +++ b/unittests/InstructionCountCI/FlagM/x87-HalfLife.json @@ -1434,7 +1434,7 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q3, [x28, #2912]", + "ldr q3, [x28, #2944]", "bic v2.16b, v2.16b, v3.16b", "ldr s3, [x4]", "mrs x0, nzcv", @@ -1463,7 +1463,7 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "mov v3.16b, v0.16b", - "ldr q4, [x28, #2912]", + "ldr q4, [x28, #2944]", "bic v3.16b, v3.16b, v4.16b", "strb wzr, [x28, #1017]", "mrs x0, nzcv", @@ -1532,7 +1532,7 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "mov v3.16b, v0.16b", - "ldr q4, [x28, #2912]", + "ldr q4, [x28, #2944]", "bic v3.16b, v3.16b, v4.16b", "ldr s4, [x4, #4]", "mrs x0, nzcv", @@ -1561,7 +1561,7 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "mov v4.16b, v0.16b", - "ldr q5, [x28, #2912]", + "ldr q5, [x28, #2944]", "bic v4.16b, v4.16b, v5.16b", "strb wzr, [x28, #1017]", "mrs x0, nzcv", @@ -1629,7 +1629,7 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "mov v4.16b, v0.16b", - "ldr q5, [x28, #2912]", + "ldr q5, [x28, #2944]", "bic v4.16b, v4.16b, v5.16b", "ldr s5, [x4, #8]", "mrs x0, nzcv", @@ -1658,7 +1658,7 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "mov v5.16b, v0.16b", - "ldr q6, [x28, #2912]", + "ldr q6, [x28, #2944]", "bic v5.16b, v5.16b, v6.16b", "strb wzr, [x28, #1017]", "mrs x0, nzcv", @@ -2968,7 +2968,7 @@ "lsl w20, w23, w20", "bic w20, w22, w20", "strb w20, [x28, #1298]", - "ldr x0, [x28, #2344]", + "ldr x0, [x28, #2376]", "ubfiz x3, x21, #4, #20", "add x0, x0, x3", "ldp x1, x0, [x0]" @@ -3939,7 +3939,7 @@ "lsl w20, w21, w20", "bic w20, w23, w20", "strb w20, [x28, #1298]", - "ldr x0, [x28, #2344]", + "ldr x0, [x28, #2376]", "ubfiz x3, x22, #4, #20", "add x0, x0, x3", "ldp x1, x0, [x0]" @@ -5964,7 +5964,7 @@ "movk w21, #0x6, lsl #16", "add w21, w20, w21", "str w20, [x8, #-4]!", - "ldr x0, [x28, #2344]", + "ldr x0, [x28, #2376]", "ubfiz x3, x21, #4, #20", "add x0, x0, x3", "ldp x1, x0, [x0]" @@ -6248,7 +6248,7 @@ "movk w21, #0x6, lsl #16", "add w21, w20, w21", "str w20, [x8, #-4]!", - "ldr x0, [x28, #2344]", + "ldr x0, [x28, #2376]", "ubfiz x3, x21, #4, #20", "add x0, x0, x3", "ldp x1, x0, [x0]" @@ -6407,7 +6407,7 @@ "movk w21, #0x1, lsl #16", "add w21, w20, w21", "str w20, [x8, #-4]!", - "ldr x0, [x28, #2344]", + "ldr x0, [x28, #2376]", "ubfiz x3, x21, #4, #20", "add x0, x0, x3", "ldp x1, x0, [x0]" diff --git a/unittests/InstructionCountCI/FlagM/x87-Oblivion.json b/unittests/InstructionCountCI/FlagM/x87-Oblivion.json index 102f608050..fe3b360cd4 100644 --- a/unittests/InstructionCountCI/FlagM/x87-Oblivion.json +++ b/unittests/InstructionCountCI/FlagM/x87-Oblivion.json @@ -10458,7 +10458,7 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q9, [x28, #2912]", + "ldr q9, [x28, #2944]", "eor v2.16b, v2.16b, v9.16b", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -10622,7 +10622,7 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q9, [x28, #2912]", + "ldr q9, [x28, #2944]", "eor v2.16b, v2.16b, v9.16b", "ldr s9, [x8, #28]", "mrs x0, nzcv", @@ -11165,7 +11165,7 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q9, [x28, #2912]", + "ldr q9, [x28, #2944]", "eor v2.16b, v2.16b, v9.16b", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -11329,7 +11329,7 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q9, [x28, #2912]", + "ldr q9, [x28, #2944]", "eor v2.16b, v2.16b, v9.16b", "ldr s9, [x8, #60]", "mrs x0, nzcv", @@ -11952,7 +11952,7 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q9, [x28, #2912]", + "ldr q9, [x28, #2944]", "eor v2.16b, v2.16b, v9.16b", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -12011,7 +12011,7 @@ "ldp x17, x30, [sp], #16", "mov v9.16b, v0.16b", "str s2, [x8, #176]", - "ldr q2, [x28, #2912]", + "ldr q2, [x28, #2944]", "eor v2.16b, v9.16b, v2.16b", "ldr s9, [x8, #8]", "mrs x0, nzcv", @@ -22845,7 +22845,7 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "mov v6.16b, v0.16b", - "ldr q8, [x28, #2912]", + "ldr q8, [x28, #2944]", "eor v6.16b, v6.16b, v8.16b", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -23145,7 +23145,7 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "mov v6.16b, v0.16b", - "ldr q9, [x28, #2912]", + "ldr q9, [x28, #2944]", "eor v6.16b, v6.16b, v9.16b", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -23336,7 +23336,7 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "mov v6.16b, v0.16b", - "ldr q9, [x28, #2912]", + "ldr q9, [x28, #2944]", "eor v6.16b, v6.16b, v9.16b", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -24236,7 +24236,7 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "mov v5.16b, v0.16b", - "ldr q7, [x28, #2912]", + "ldr q7, [x28, #2944]", "eor v5.16b, v5.16b, v7.16b", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -24752,7 +24752,7 @@ "ldp x17, x30, [sp], #16", "fmov s3, s0", "str s3, [x4, #1024]", - "ldr q3, [x28, #2912]", + "ldr q3, [x28, #2944]", "eor v2.16b, v2.16b, v3.16b", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -24808,7 +24808,7 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q3, [x28, #2912]", + "ldr q3, [x28, #2944]", "eor v2.16b, v2.16b, v3.16b", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -24838,7 +24838,7 @@ "fmov s2, s0", "str s2, [x4, #1152]", "strb wzr, [x28, #1017]", - "ldr q2, [x28, #2912]", + "ldr q2, [x28, #2944]", "eor v2.16b, v4.16b, v2.16b", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -24894,7 +24894,7 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q3, [x28, #2912]", + "ldr q3, [x28, #2944]", "eor v2.16b, v2.16b, v3.16b", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -24950,7 +24950,7 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q3, [x28, #2912]", + "ldr q3, [x28, #2944]", "eor v2.16b, v2.16b, v3.16b", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -24980,7 +24980,7 @@ "fmov s2, s0", "str s2, [x4, #1344]", "strb wzr, [x28, #1017]", - "ldr q2, [x28, #2912]", + "ldr q2, [x28, #2944]", "eor v2.16b, v9.16b, v2.16b", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -25036,7 +25036,7 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q3, [x28, #2912]", + "ldr q3, [x28, #2944]", "eor v2.16b, v2.16b, v3.16b", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -25066,7 +25066,7 @@ "fmov s2, s0", "str s2, [x4, #1472]", "strb wzr, [x28, #1017]", - "ldr q2, [x28, #2912]", + "ldr q2, [x28, #2944]", "eor v2.16b, v8.16b, v2.16b", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -25096,7 +25096,7 @@ "fmov s2, s0", "str s2, [x4, #1536]", "strb wzr, [x28, #1017]", - "ldr q2, [x28, #2912]", + "ldr q2, [x28, #2944]", "eor v2.16b, v7.16b, v2.16b", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -25126,7 +25126,7 @@ "fmov s2, s0", "str s2, [x4, #1600]", "strb wzr, [x28, #1017]", - "ldr q2, [x28, #2912]", + "ldr q2, [x28, #2944]", "eor v2.16b, v6.16b, v2.16b", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -25155,7 +25155,7 @@ "ldp x17, x30, [sp], #16", "fmov s2, s0", "str s2, [x4, #1664]", - "ldr q2, [x28, #2912]", + "ldr q2, [x28, #2944]", "eor v2.16b, v5.16b, v2.16b", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -37880,7 +37880,7 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "mov v2.16b, v0.16b", - "ldr q3, [x28, #2912]", + "ldr q3, [x28, #2944]", "eor v3.16b, v2.16b, v3.16b", "ldr s4, [x4]", "mrs x0, nzcv", @@ -38017,7 +38017,7 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "mov v4.16b, v0.16b", - "ldr q5, [x28, #2912]", + "ldr q5, [x28, #2944]", "eor v5.16b, v4.16b, v5.16b", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -38128,7 +38128,7 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "mov v5.16b, v0.16b", - "ldr q6, [x28, #2912]", + "ldr q6, [x28, #2944]", "eor v6.16b, v5.16b, v6.16b", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -38239,7 +38239,7 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "mov v6.16b, v0.16b", - "ldr q7, [x28, #2912]", + "ldr q7, [x28, #2944]", "eor v7.16b, v6.16b, v7.16b", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -38350,7 +38350,7 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "mov v7.16b, v0.16b", - "ldr q8, [x28, #2912]", + "ldr q8, [x28, #2944]", "eor v8.16b, v7.16b, v8.16b", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -38461,7 +38461,7 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "mov v8.16b, v0.16b", - "ldr q9, [x28, #2912]", + "ldr q9, [x28, #2944]", "eor v9.16b, v8.16b, v9.16b", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -38572,7 +38572,7 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "mov v9.16b, v0.16b", - "ldr q10, [x28, #2912]", + "ldr q10, [x28, #2944]", "eor v9.16b, v9.16b, v10.16b", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -38682,7 +38682,7 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "mov v9.16b, v0.16b", - "ldr q10, [x28, #2912]", + "ldr q10, [x28, #2944]", "eor v9.16b, v9.16b, v10.16b", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -38792,7 +38792,7 @@ "ldr x16, [sp], #16", "ldp x17, x30, [sp], #16", "mov v9.16b, v0.16b", - "ldr q10, [x28, #2912]", + "ldr q10, [x28, #2944]", "eor v9.16b, v9.16b, v10.16b", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -52965,7 +52965,7 @@ "lsl w20, w22, w20", "bic w20, w23, w20", "strb w20, [x28, #1298]", - "ldr x0, [x28, #2344]", + "ldr x0, [x28, #2376]", "ubfiz x3, x21, #4, #20", "add x0, x0, x3", "ldp x1, x0, [x0]" @@ -55086,7 +55086,7 @@ "lsl w20, w23, w20", "bic w20, w22, w20", "strb w20, [x28, #1298]", - "ldr x0, [x28, #2344]", + "ldr x0, [x28, #2376]", "ubfiz x3, x21, #4, #20", "add x0, x0, x3", "ldp x1, x0, [x0]" @@ -55474,7 +55474,7 @@ "mov x8, x26", "str s2, [x8, #16]", "uxtb w7, w4", - "ldr q2, [x28, #2688]", + "ldr q2, [x28, #2720]", "str w7, [x8, #56]", "mrs x0, nzcv", "str w0, [x28, #1000]", @@ -55732,7 +55732,7 @@ "lsl w20, w23, w20", "bic w20, w22, w20", "strb w20, [x28, #1298]", - "ldr x0, [x28, #2344]", + "ldr x0, [x28, #2376]", "ubfiz x3, x21, #4, #20", "add x0, x0, x3", "ldp x1, x0, [x0]" @@ -56113,7 +56113,7 @@ "lsl w20, w23, w20", "bic w20, w22, w20", "strb w20, [x28, #1298]", - "ldr x0, [x28, #2344]", + "ldr x0, [x28, #2376]", "ubfiz x3, x21, #4, #20", "add x0, x0, x3", "ldp x1, x0, [x0]" @@ -60332,7 +60332,7 @@ "strb w21, [x28, #1298]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "ldr q3, [x28, #2912]", + "ldr q3, [x28, #2944]", "eor v2.16b, v2.16b, v3.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -60574,7 +60574,7 @@ "strb w21, [x28, #1298]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "ldr q3, [x28, #2912]", + "ldr q3, [x28, #2944]", "eor v2.16b, v2.16b, v3.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -60852,7 +60852,7 @@ "strb w23, [x28, #1298]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "ldr q3, [x28, #2912]", + "ldr q3, [x28, #2944]", "eor v2.16b, v2.16b, v3.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -61425,7 +61425,7 @@ "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "ldr q3, [x28, #2912]", + "ldr q3, [x28, #2944]", "eor v2.16b, v2.16b, v3.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -61518,7 +61518,7 @@ "strb wzr, [x28, #1017]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "ldr q3, [x28, #2912]", + "ldr q3, [x28, #2944]", "eor v2.16b, v2.16b, v3.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -61647,7 +61647,7 @@ "strb w21, [x28, #1298]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "ldr q3, [x28, #2912]", + "ldr q3, [x28, #2944]", "eor v2.16b, v2.16b, v3.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -70317,7 +70317,7 @@ "lsl w20, w22, w20", "orr w20, w23, w20", "strb w20, [x28, #1298]", - "ldr x0, [x28, #2344]", + "ldr x0, [x28, #2376]", "ubfiz x3, x21, #4, #20", "add x0, x0, x3", "ldp x1, x0, [x0]" @@ -70972,7 +70972,7 @@ "movk w21, #0x79, lsl #16", "add w21, w20, w21", "str w20, [x8, #-4]!", - "ldr x0, [x28, #2344]", + "ldr x0, [x28, #2376]", "ubfiz x3, x21, #4, #20", "add x0, x0, x3", "ldp x1, x0, [x0]" diff --git a/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json b/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json index c42f8b69f5..58bcc90c0f 100644 --- a/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json +++ b/unittests/InstructionCountCI/FlagM/x87-Psychonauts.json @@ -30360,7 +30360,7 @@ "add w21, w20, w21", "str w20, [x8, #-4]!", "cfinv", - "ldr x0, [x28, #2344]", + "ldr x0, [x28, #2376]", "ubfiz x3, x21, #4, #20", "add x0, x0, x3", "ldp x1, x0, [x0]" @@ -31524,7 +31524,7 @@ "strb w21, [x28, #1298]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "ldr q3, [x28, #2912]", + "ldr q3, [x28, #2944]", "eor v2.16b, v2.16b, v3.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -31696,7 +31696,7 @@ "strb w21, [x28, #1298]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "ldr q3, [x28, #2912]", + "ldr q3, [x28, #2944]", "eor v2.16b, v2.16b, v3.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -32186,7 +32186,7 @@ "strb w21, [x28, #1298]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "ldr q3, [x28, #2912]", + "ldr q3, [x28, #2944]", "eor v2.16b, v2.16b, v3.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -37126,7 +37126,7 @@ "ldr w9, [x8, #48]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "ldr q3, [x28, #2912]", + "ldr q3, [x28, #2944]", "eor v2.16b, v2.16b, v3.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -37622,7 +37622,7 @@ "ldr w9, [x8, #48]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "ldr q3, [x28, #2912]", + "ldr q3, [x28, #2944]", "eor v2.16b, v2.16b, v3.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -43608,7 +43608,7 @@ "strb w21, [x28, #1298]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "ldr q3, [x28, #2912]", + "ldr q3, [x28, #2944]", "eor v2.16b, v2.16b, v3.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -61964,7 +61964,7 @@ "add w21, w20, w21", "str w20, [x8, #-4]!", "strb wzr, [x28, #1298]", - "ldr x0, [x28, #2344]", + "ldr x0, [x28, #2376]", "ubfiz x3, x21, #4, #20", "add x0, x0, x3", "ldp x1, x0, [x0]" @@ -69472,7 +69472,7 @@ "add w21, w20, w21", "str w20, [x8, #-4]!", "strb wzr, [x28, #1298]", - "ldr x0, [x28, #2344]", + "ldr x0, [x28, #2376]", "ubfiz x3, x21, #4, #20", "add x0, x0, x3", "ldp x1, x0, [x0]" @@ -70500,7 +70500,7 @@ "strb w22, [x28, #1298]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "ldr q3, [x28, #2912]", + "ldr q3, [x28, #2944]", "eor v2.16b, v2.16b, v3.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -73062,7 +73062,7 @@ "strb w22, [x28, #1298]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "ldr q3, [x28, #2912]", + "ldr q3, [x28, #2944]", "eor v2.16b, v2.16b, v3.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -74985,7 +74985,7 @@ "strb w22, [x28, #1298]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "ldr q3, [x28, #2912]", + "ldr q3, [x28, #2944]", "eor v2.16b, v2.16b, v3.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -75376,7 +75376,7 @@ "strb w22, [x28, #1298]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "ldr q3, [x28, #2912]", + "ldr q3, [x28, #2944]", "eor v2.16b, v2.16b, v3.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -83262,7 +83262,7 @@ "strb w22, [x28, #1298]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "ldr q3, [x28, #2912]", + "ldr q3, [x28, #2944]", "eor v2.16b, v2.16b, v3.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", @@ -92554,7 +92554,7 @@ "lsl w20, w23, w20", "bic w20, w22, w20", "strb w20, [x28, #1298]", - "ldr x0, [x28, #2344]", + "ldr x0, [x28, #2376]", "ubfiz x3, x21, #4, #20", "add x0, x0, x3", "ldp x1, x0, [x0]" diff --git a/unittests/InstructionCountCI/FlagM/x87.json b/unittests/InstructionCountCI/FlagM/x87.json index 5de9bd8b45..068e39a678 100644 --- a/unittests/InstructionCountCI/FlagM/x87.json +++ b/unittests/InstructionCountCI/FlagM/x87.json @@ -4172,7 +4172,7 @@ "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "ldr q3, [x28, #2912]", + "ldr q3, [x28, #2944]", "eor v2.16b, v2.16b, v3.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" @@ -4187,7 +4187,7 @@ "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "ldr q3, [x28, #2912]", + "ldr q3, [x28, #2944]", "bic v2.16b, v2.16b, v3.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" @@ -4272,7 +4272,7 @@ "0xd9 11b 0xe8 /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2688]", + "ldr q2, [x28, #2720]", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", @@ -4292,7 +4292,7 @@ "0xd9 11b 0xe9 /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2704]", + "ldr q2, [x28, #2736]", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", @@ -4312,7 +4312,7 @@ "0xd9 11b 0xea /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2720]", + "ldr q2, [x28, #2752]", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", @@ -4332,7 +4332,7 @@ "0xd9 11b 0xeb /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2736]", + "ldr q2, [x28, #2768]", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", @@ -4352,7 +4352,7 @@ "0xd9 11b 0xec /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2752]", + "ldr q2, [x28, #2784]", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", @@ -4372,7 +4372,7 @@ "0xd9 11b 0xed /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2768]", + "ldr q2, [x28, #2800]", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", @@ -4529,7 +4529,7 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldr q2, [x28, #2688]", + "ldr q2, [x28, #2720]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -4799,7 +4799,7 @@ "0xd9 11b 0xf9 /7" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2688]", + "ldr q2, [x28, #2720]", "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]", diff --git a/unittests/InstructionCountCI/H0F38.json b/unittests/InstructionCountCI/H0F38.json index 127478263d..d4aeca8b55 100644 --- a/unittests/InstructionCountCI/H0F38.json +++ b/unittests/InstructionCountCI/H0F38.json @@ -655,7 +655,7 @@ "0x66 0x0f 0x38 0x41" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2368]", + "ldr q2, [x28, #2400]", "zip1 v3.8h, v2.8h, v17.8h", "zip2 v2.8h, v2.8h, v17.8h", "umin v2.4s, v3.4s, v2.4s", diff --git a/unittests/InstructionCountCI/H0F3A.json b/unittests/InstructionCountCI/H0F3A.json index 614ac04a77..998824c464 100644 --- a/unittests/InstructionCountCI/H0F3A.json +++ b/unittests/InstructionCountCI/H0F3A.json @@ -321,7 +321,7 @@ "0x66 0x0f 0x3a 0x0c" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2560]", + "ldr q2, [x28, #2592]", "tbx v16.16b, {v17.16b}, v2.16b" ] }, @@ -331,7 +331,7 @@ "0x66 0x0f 0x3a 0x0c" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2576]", + "ldr q2, [x28, #2608]", "tbx v16.16b, {v17.16b}, v2.16b" ] }, @@ -350,7 +350,7 @@ "0x66 0x0f 0x3a 0x0c" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2592]", + "ldr q2, [x28, #2624]", "tbx v16.16b, {v17.16b}, v2.16b" ] }, @@ -370,7 +370,7 @@ "0x66 0x0f 0x3a 0x0c" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2608]", + "ldr q2, [x28, #2640]", "tbx v16.16b, {v17.16b}, v2.16b" ] }, @@ -389,7 +389,7 @@ "0x66 0x0f 0x3a 0x0c" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2624]", + "ldr q2, [x28, #2656]", "tbx v16.16b, {v17.16b}, v2.16b" ] }, @@ -399,7 +399,7 @@ "0x66 0x0f 0x3a 0x0c" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2640]", + "ldr q2, [x28, #2672]", "tbx v16.16b, {v17.16b}, v2.16b" ] }, @@ -468,7 +468,7 @@ "0x66 0x0f 0x3a 0x0e" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2096]", + "ldr x0, [x28, #2128]", "ldr q2, [x0, #3440]", "tbx v16.16b, {v17.16b}, v2.16b" ] diff --git a/unittests/InstructionCountCI/PrimaryGroup.json b/unittests/InstructionCountCI/PrimaryGroup.json index c10914eaef..6ea45482a1 100644 --- a/unittests/InstructionCountCI/PrimaryGroup.json +++ b/unittests/InstructionCountCI/PrimaryGroup.json @@ -2825,7 +2825,7 @@ "mov x0, x5", "mov x1, x4", "mov x2, x6", - "ldr x3, [x28, #2960]", + "ldr x3, [x28, #3056]", "str x30, [sp, #-16]!", "blr x3", "ldr x30, [sp], #16", @@ -2836,7 +2836,7 @@ "mov x0, x5", "mov x1, x4", "mov x2, x6", - "ldr x3, [x28, #2976]", + "ldr x3, [x28, #3072]", "str x30, [sp, #-16]!", "blr x3", "ldr x30, [sp], #16", @@ -2894,7 +2894,7 @@ "mov x0, x5", "mov x1, x4", "mov x2, x6", - "ldr x3, [x28, #2968]", + "ldr x3, [x28, #3064]", "str x30, [sp, #-16]!", "blr x3", "ldr x30, [sp], #16", @@ -2907,7 +2907,7 @@ "mov x0, x5", "mov x1, x4", "mov x2, x6", - "ldr x3, [x28, #2984]", + "ldr x3, [x28, #3080]", "str x30, [sp, #-16]!", "blr x3", "ldr x30, [sp], #16", diff --git a/unittests/InstructionCountCI/Secondary.json b/unittests/InstructionCountCI/Secondary.json index cdd2d346cd..474037ddbc 100644 --- a/unittests/InstructionCountCI/Secondary.json +++ b/unittests/InstructionCountCI/Secondary.json @@ -174,8 +174,8 @@ "strb wzr, [x28, #1019]", "mov w20, #0xffff", "ldr d2, [x4]", - "ldr d3, [x28, #2880]", - "ldr d4, [x28, #2784]", + "ldr d3, [x28, #2912]", + "ldr d4, [x28, #2816]", "fcvtzs v5.2s, v2.2s", "fcmgt v2.4s, v4.4s, v2.4s", "bsl v2.8b, v5.8b, v3.8b", @@ -188,8 +188,8 @@ "ExpectedInstructionCount": 8, "Comment": "0x0f 0x2c", "ExpectedArm64ASM": [ - "ldr d2, [x28, #2880]", - "ldr d3, [x28, #2784]", + "ldr d2, [x28, #2912]", + "ldr d3, [x28, #2816]", "fcvtzs v4.2s, v16.2s", "fcmgt v3.4s, v3.4s, v16.4s", "bit v2.8b, v4.8b, v3.8b", @@ -204,8 +204,8 @@ "ExpectedArm64ASM": [ "ldr d2, [x4]", "frinti v2.4s, v2.4s", - "ldr d3, [x28, #2880]", - "ldr d4, [x28, #2784]", + "ldr d3, [x28, #2912]", + "ldr d4, [x28, #2816]", "fcvtzs v5.2s, v2.2s", "fcmgt v2.4s, v4.4s, v2.4s", "bsl v2.8b, v5.8b, v3.8b", @@ -219,8 +219,8 @@ "Comment": "0x0f 0x2d", "ExpectedArm64ASM": [ "frinti v2.4s, v16.4s", - "ldr d3, [x28, #2880]", - "ldr d4, [x28, #2784]", + "ldr d3, [x28, #2912]", + "ldr d4, [x28, #2816]", "fcvtzs v5.2s, v2.2s", "fcmgt v2.4s, v4.4s, v2.4s", "bsl v2.8b, v5.8b, v3.8b", @@ -654,7 +654,7 @@ "Comment": "0x0f 0x50", "ExpectedArm64ASM": [ "ushr v2.4s, v16.4s, #31", - "ldr q3, [x28, #2528]", + "ldr q3, [x28, #2560]", "ushl v2.4s, v2.4s, v3.4s", "addv s2, v2.4s", "mov w4, v2.s[0]" @@ -665,7 +665,7 @@ "Comment": "0x0f 0x50", "ExpectedArm64ASM": [ "ushr v2.4s, v16.4s, #31", - "ldr q3, [x28, #2528]", + "ldr q3, [x28, #2560]", "ushl v2.4s, v2.4s, v3.4s", "addv s2, v2.4s", "mov w4, v2.s[0]" @@ -1108,7 +1108,7 @@ "Comment": "0x0f 0x70", "ExpectedArm64ASM": [ "ldr d2, [x28, #1056]", - "ldr x0, [x28, #2048]", + "ldr x0, [x28, #2080]", "ldr d3, [x0, #16]", "tbl v2.8b, {v2.16b}, v3.8b", "str d2, [x28, #1040]", @@ -1121,7 +1121,7 @@ "Comment": "0x0f 0x70", "ExpectedArm64ASM": [ "ldr d2, [x4]", - "ldr x0, [x28, #2048]", + "ldr x0, [x28, #2080]", "ldr d3, [x0, #16]", "tbl v2.8b, {v2.16b}, v3.8b", "str d2, [x28, #1040]", @@ -3400,7 +3400,7 @@ "ExpectedInstructionCount": 3, "Comment": "0x0f 0xc6", "ExpectedArm64ASM": [ - "ldr x0, [x28, #2072]", + "ldr x0, [x28, #2104]", "ldr q2, [x0, #16]", "tbl v16.16b, {v16.16b, v17.16b}, v2.16b" ] @@ -3409,7 +3409,7 @@ "ExpectedInstructionCount": 5, "Comment": "0x0f 0xc6", "ExpectedArm64ASM": [ - "ldr x0, [x28, #2072]", + "ldr x0, [x28, #2104]", "ldr q2, [x0, #16]", "mov v0.16b, v17.16b", "mov v1.16b, v16.16b", @@ -3421,7 +3421,7 @@ "Comment": "0x0f 0xc6", "ExpectedArm64ASM": [ "ldr q2, [x4]", - "ldr x0, [x28, #2072]", + "ldr x0, [x28, #2104]", "ldr q3, [x0, #16]", "mov v0.16b, v16.16b", "mov v1.16b, v2.16b", @@ -3529,7 +3529,7 @@ "Comment": "0x0f 0xd7", "ExpectedArm64ASM": [ "ldr d2, [x28, #1040]", - "ldr d3, [x28, #2656]", + "ldr d3, [x28, #2688]", "cmlt v2.16b, v2.16b, #0", "and v2.16b, v2.16b, v3.16b", "addp v2.16b, v2.16b, v2.16b", diff --git a/unittests/InstructionCountCI/Secondary_OpSize.json b/unittests/InstructionCountCI/Secondary_OpSize.json index 2077b3b8b5..efcc384e1c 100644 --- a/unittests/InstructionCountCI/Secondary_OpSize.json +++ b/unittests/InstructionCountCI/Secondary_OpSize.json @@ -126,8 +126,8 @@ "ExpectedInstructionCount": 11, "Comment": "0x66 0x0f 0x2c", "ExpectedArm64ASM": [ - "ldr d2, [x28, #2880]", - "ldr q3, [x28, #2832]", + "ldr d2, [x28, #2912]", + "ldr q3, [x28, #2864]", "frintz v4.2d, v16.2d", "fcvtn v4.2s, v4.2d", "fcvtzs v4.2s, v4.2s", @@ -144,8 +144,8 @@ "Comment": "0x66 0x0f 0x2d", "ExpectedArm64ASM": [ "frinti v2.2d, v16.2d", - "ldr d3, [x28, #2880]", - "ldr q4, [x28, #2832]", + "ldr d3, [x28, #2912]", + "ldr q4, [x28, #2864]", "frintz v5.2d, v2.2d", "fcvtn v5.2s, v5.2d", "fcvtzs v5.2s, v5.2s", @@ -230,8 +230,8 @@ "Comment": "0x66 0x0f 0x5b", "ExpectedArm64ASM": [ "frinti v2.4s, v17.4s", - "ldr q3, [x28, #2880]", - "ldr q4, [x28, #2784]", + "ldr q3, [x28, #2912]", + "ldr q4, [x28, #2816]", "fcvtzs v5.4s, v2.4s", "fcmgt v2.4s, v4.4s, v2.4s", "mov v16.16b, v2.16b", @@ -244,8 +244,8 @@ "ExpectedArm64ASM": [ "ldr q2, [x4]", "frinti v2.4s, v2.4s", - "ldr q3, [x28, #2880]", - "ldr q4, [x28, #2784]", + "ldr q3, [x28, #2912]", + "ldr q4, [x28, #2816]", "fcvtzs v5.4s, v2.4s", "fcmgt v2.4s, v4.4s, v2.4s", "mov v16.16b, v2.16b", @@ -537,7 +537,7 @@ "0x66 0x0f 0x70" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2064]", + "ldr x0, [x28, #2096]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b}, v2.16b" ] @@ -551,7 +551,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x4]", - "ldr x0, [x28, #2064]", + "ldr x0, [x28, #2096]", "ldr q3, [x0, #16]", "tbl v16.16b, {v2.16b}, v3.16b" ] @@ -689,7 +689,7 @@ ], "ExpectedArm64ASM": [ "ldr q2, [x4]", - "ldr x0, [x28, #2064]", + "ldr x0, [x28, #2096]", "ldr q3, [x0, #2480]", "tbl v16.16b, {v2.16b}, v3.16b" ] @@ -1241,7 +1241,7 @@ "ExpectedInstructionCount": 3, "Comment": "0x66 0x0f 0xd0", "ExpectedArm64ASM": [ - "ldr q2, [x28, #2432]", + "ldr q2, [x28, #2464]", "eor v2.16b, v17.16b, v2.16b", "fadd v16.2d, v16.2d, v2.2d" ] @@ -1297,7 +1297,7 @@ "ExpectedInstructionCount": 7, "Comment": "0x66 0x0f 0xd7", "ExpectedArm64ASM": [ - "ldr q2, [x28, #2656]", + "ldr q2, [x28, #2688]", "cmlt v3.16b, v16.16b, #0", "and v2.16b, v3.16b, v2.16b", "addp v2.16b, v2.16b, v2.16b", @@ -1420,8 +1420,8 @@ "ExpectedInstructionCount": 9, "Comment": "0x66 0x0f 0xe6", "ExpectedArm64ASM": [ - "ldr d2, [x28, #2880]", - "ldr q3, [x28, #2832]", + "ldr d2, [x28, #2912]", + "ldr q3, [x28, #2864]", "frintz v4.2d, v17.2d", "fcvtn v4.2s, v4.2d", "fcvtzs v4.2s, v4.2s", diff --git a/unittests/InstructionCountCI/Secondary_REP.json b/unittests/InstructionCountCI/Secondary_REP.json index 6717ce93ac..5af516966c 100644 --- a/unittests/InstructionCountCI/Secondary_REP.json +++ b/unittests/InstructionCountCI/Secondary_REP.json @@ -116,7 +116,7 @@ "ExpectedArm64ASM": [ "fcvtzs w20, s16", "mov w21, #0x80000000", - "ldr s2, [x28, #2784]", + "ldr s2, [x28, #2816]", "mrs x22, nzcv", "fcmp s2, s16", "csel w4, w20, w21, gt", @@ -130,7 +130,7 @@ "ldr s2, [x6]", "fcvtzs w20, s2", "mov w21, #0x80000000", - "ldr s3, [x28, #2784]", + "ldr s3, [x28, #2816]", "mrs x22, nzcv", "fcmp s3, s2", "csel w4, w20, w21, gt", @@ -143,7 +143,7 @@ "ExpectedArm64ASM": [ "fcvtzs x20, s16", "mov x21, #0x8000000000000000", - "ldr s2, [x28, #2816]", + "ldr s2, [x28, #2848]", "mrs x22, nzcv", "fcmp s2, s16", "csel x4, x20, x21, gt", @@ -157,7 +157,7 @@ "ldr d2, [x6]", "fcvtzs x20, s2", "mov x21, #0x8000000000000000", - "ldr s3, [x28, #2816]", + "ldr s3, [x28, #2848]", "mrs x22, nzcv", "fcmp s3, s2", "csel x4, x20, x21, gt", @@ -171,7 +171,7 @@ "frinti s2, s16", "fcvtzs w20, s2", "mov w21, #0x80000000", - "ldr s3, [x28, #2784]", + "ldr s3, [x28, #2816]", "mrs x22, nzcv", "fcmp s3, s2", "csel w4, w20, w21, gt", @@ -186,7 +186,7 @@ "frinti s2, s2", "fcvtzs w20, s2", "mov w21, #0x80000000", - "ldr s3, [x28, #2784]", + "ldr s3, [x28, #2816]", "mrs x22, nzcv", "fcmp s3, s2", "csel w4, w20, w21, gt", @@ -200,7 +200,7 @@ "frinti s2, s16", "fcvtzs x20, s2", "mov x21, #0x8000000000000000", - "ldr s3, [x28, #2816]", + "ldr s3, [x28, #2848]", "mrs x22, nzcv", "fcmp s3, s2", "csel x4, x20, x21, gt", @@ -215,7 +215,7 @@ "frinti s2, s2", "fcvtzs x20, s2", "mov x21, #0x8000000000000000", - "ldr s3, [x28, #2816]", + "ldr s3, [x28, #2848]", "mrs x22, nzcv", "fcmp s3, s2", "csel x4, x20, x21, gt", @@ -294,8 +294,8 @@ "ExpectedInstructionCount": 6, "Comment": "0xf3 0x0f 0x5b", "ExpectedArm64ASM": [ - "ldr q2, [x28, #2880]", - "ldr q3, [x28, #2784]", + "ldr q2, [x28, #2912]", + "ldr q3, [x28, #2816]", "fcvtzs v4.4s, v17.4s", "fcmgt v3.4s, v3.4s, v17.4s", "mov v16.16b, v3.16b", @@ -395,7 +395,7 @@ "0xf3 0x0f 0x70" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2056]", + "ldr x0, [x28, #2088]", "ldr q2, [x0, #1280]", "tbl v16.16b, {v17.16b}, v2.16b" ] @@ -408,7 +408,7 @@ "0xf3 0x0f 0x70" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2056]", + "ldr x0, [x28, #2088]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b}, v2.16b" ] diff --git a/unittests/InstructionCountCI/Secondary_REPNE.json b/unittests/InstructionCountCI/Secondary_REPNE.json index 351740ce77..35074a3f1f 100644 --- a/unittests/InstructionCountCI/Secondary_REPNE.json +++ b/unittests/InstructionCountCI/Secondary_REPNE.json @@ -101,7 +101,7 @@ "ExpectedArm64ASM": [ "fcvtzs w20, d16", "mov w21, #0x80000000", - "ldr d2, [x28, #2832]", + "ldr d2, [x28, #2864]", "mrs x22, nzcv", "fcmp d2, d16", "csel w4, w20, w21, gt", @@ -115,7 +115,7 @@ "ldr d2, [x6]", "fcvtzs w20, d2", "mov w21, #0x80000000", - "ldr d3, [x28, #2832]", + "ldr d3, [x28, #2864]", "mrs x22, nzcv", "fcmp d3, d2", "csel w4, w20, w21, gt", @@ -128,7 +128,7 @@ "ExpectedArm64ASM": [ "fcvtzs x20, d16", "mov x21, #0x8000000000000000", - "ldr d2, [x28, #2864]", + "ldr d2, [x28, #2896]", "mrs x22, nzcv", "fcmp d2, d16", "csel x4, x20, x21, gt", @@ -142,7 +142,7 @@ "ldr d2, [x6]", "fcvtzs x20, d2", "mov x21, #0x8000000000000000", - "ldr d3, [x28, #2864]", + "ldr d3, [x28, #2896]", "mrs x22, nzcv", "fcmp d3, d2", "csel x4, x20, x21, gt", @@ -156,7 +156,7 @@ "frinti d2, d16", "fcvtzs x20, d2", "mov x21, #0x8000000000000000", - "ldr d3, [x28, #2864]", + "ldr d3, [x28, #2896]", "mrs x22, nzcv", "fcmp d3, d2", "csel x4, x20, x21, gt", @@ -171,7 +171,7 @@ "frinti d2, d2", "fcvtzs x20, d2", "mov x21, #0x8000000000000000", - "ldr d3, [x28, #2864]", + "ldr d3, [x28, #2896]", "mrs x22, nzcv", "fcmp d3, d2", "csel x4, x20, x21, gt", @@ -185,7 +185,7 @@ "frinti d2, d16", "fcvtzs x20, d2", "mov x21, #0x8000000000000000", - "ldr d3, [x28, #2864]", + "ldr d3, [x28, #2896]", "mrs x22, nzcv", "fcmp d3, d2", "csel x4, x20, x21, gt", @@ -200,7 +200,7 @@ "frinti d2, d2", "fcvtzs x20, d2", "mov x21, #0x8000000000000000", - "ldr d3, [x28, #2864]", + "ldr d3, [x28, #2896]", "mrs x22, nzcv", "fcmp d3, d2", "csel x4, x20, x21, gt", @@ -332,7 +332,7 @@ "0xf2 0x0f 0x70" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2048]", + "ldr x0, [x28, #2080]", "ldr q2, [x0, #1280]", "tbl v16.16b, {v17.16b}, v2.16b" ] @@ -345,7 +345,7 @@ "0xf2 0x0f 0x70" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2048]", + "ldr x0, [x28, #2080]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b}, v2.16b" ] @@ -501,7 +501,7 @@ "ExpectedInstructionCount": 3, "Comment": "0xf2 0x0f 0xd0", "ExpectedArm64ASM": [ - "ldr q2, [x28, #2400]", + "ldr q2, [x28, #2432]", "eor v2.16b, v17.16b, v2.16b", "fadd v16.4s, v16.4s, v2.4s" ] @@ -520,8 +520,8 @@ "Comment": "0xf2 0x0f 0xe6", "ExpectedArm64ASM": [ "frinti v2.2d, v17.2d", - "ldr d3, [x28, #2880]", - "ldr q4, [x28, #2832]", + "ldr d3, [x28, #2912]", + "ldr q4, [x28, #2864]", "frintz v5.2d, v2.2d", "fcvtn v5.2s, v5.2d", "fcvtzs v5.2s, v5.2s", diff --git a/unittests/InstructionCountCI/Secondary_REPNE_SVE128.json b/unittests/InstructionCountCI/Secondary_REPNE_SVE128.json index f4247cd04f..57a2599d41 100644 --- a/unittests/InstructionCountCI/Secondary_REPNE_SVE128.json +++ b/unittests/InstructionCountCI/Secondary_REPNE_SVE128.json @@ -16,8 +16,8 @@ "Comment": "0xf2 0x0f 0xe6", "ExpectedArm64ASM": [ "frinti v2.2d, v17.2d", - "ldr d3, [x28, #2880]", - "ldr q4, [x28, #2832]", + "ldr d3, [x28, #2912]", + "ldr q4, [x28, #2864]", "fcvtzs z5.s, p6/m, z2.d", "uzp1 z5.s, z5.s, z5.s", "mov v5.8b, v5.8b", diff --git a/unittests/InstructionCountCI/VEX_map1.json b/unittests/InstructionCountCI/VEX_map1.json index 2ceba4debc..1899b7acec 100644 --- a/unittests/InstructionCountCI/VEX_map1.json +++ b/unittests/InstructionCountCI/VEX_map1.json @@ -2801,7 +2801,7 @@ "Map 1 0b00 0xC6 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2072]", + "ldr x0, [x28, #2104]", "ldr q2, [x0, #16]", "tbl v16.16b, {v17.16b, v18.16b}, v2.16b" ] @@ -2870,7 +2870,7 @@ "Map 1 0b00 0xC6 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2072]", + "ldr x0, [x28, #2104]", "ldr q2, [x0, #32]", "tbl v16.16b, {v17.16b, v18.16b}, v2.16b" ] @@ -2939,7 +2939,7 @@ "Map 1 0b00 0xC6 128-bit" ], "ExpectedArm64ASM": [ - "ldr x0, [x28, #2072]", + "ldr x0, [x28, #2104]", "ldr q2, [x0, #48]", "tbl v16.16b, {v17.16b, v18.16b}, v2.16b" ] @@ -3284,7 +3284,7 @@ "ExpectedArm64ASM": [ "fcvtzs w20, s16", "mov w21, #0x80000000", - "ldr s2, [x28, #2784]", + "ldr s2, [x28, #2816]", "mrs x22, nzcv", "fcmp s2, s16", "csel w4, w20, w21, gt", @@ -3299,7 +3299,7 @@ "ExpectedArm64ASM": [ "fcvtzs x20, s16", "mov x21, #0x8000000000000000", - "ldr s2, [x28, #2816]", + "ldr s2, [x28, #2848]", "mrs x22, nzcv", "fcmp s2, s16", "csel x4, x20, x21, gt", @@ -3314,7 +3314,7 @@ "ExpectedArm64ASM": [ "fcvtzs w20, d16", "mov w21, #0x80000000", - "ldr d2, [x28, #2832]", + "ldr d2, [x28, #2864]", "mrs x22, nzcv", "fcmp d2, d16", "csel w4, w20, w21, gt", @@ -3329,7 +3329,7 @@ "ExpectedArm64ASM": [ "fcvtzs x20, d16", "mov x21, #0x8000000000000000", - "ldr d2, [x28, #2864]", + "ldr d2, [x28, #2896]", "mrs x22, nzcv", "fcmp d2, d16", "csel x4, x20, x21, gt", @@ -3345,7 +3345,7 @@ "frinti s2, s16", "fcvtzs w20, s2", "mov w21, #0x80000000", - "ldr s3, [x28, #2784]", + "ldr s3, [x28, #2816]", "mrs x22, nzcv", "fcmp s3, s2", "csel w4, w20, w21, gt", @@ -3361,7 +3361,7 @@ "frinti s2, s16", "fcvtzs x20, s2", "mov x21, #0x8000000000000000", - "ldr s3, [x28, #2816]", + "ldr s3, [x28, #2848]", "mrs x22, nzcv", "fcmp s3, s2", "csel x4, x20, x21, gt", @@ -3377,7 +3377,7 @@ "frinti d2, d16", "fcvtzs x20, d2", "mov x21, #0x8000000000000000", - "ldr d3, [x28, #2864]", + "ldr d3, [x28, #2896]", "mrs x22, nzcv", "fcmp d3, d2", "csel x4, x20, x21, gt", @@ -3393,7 +3393,7 @@ "frinti d2, d16", "fcvtzs x20, d2", "mov x21, #0x8000000000000000", - "ldr d3, [x28, #2864]", + "ldr d3, [x28, #2896]", "mrs x22, nzcv", "fcmp d3, d2", "csel x4, x20, x21, gt", @@ -3656,8 +3656,8 @@ ], "ExpectedArm64ASM": [ "frinti v2.4s, v17.4s", - "ldr q3, [x28, #2880]", - "ldr q4, [x28, #2784]", + "ldr q3, [x28, #2912]", + "ldr q4, [x28, #2816]", "fcvtzs v5.4s, v2.4s", "fcmgt v2.4s, v4.4s, v2.4s", "mov v16.16b, v2.16b", @@ -3691,8 +3691,8 @@ "Map 1 0b10 0x5b 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2880]", - "ldr q3, [x28, #2784]", + "ldr q2, [x28, #2912]", + "ldr q3, [x28, #2816]", "fcvtzs v4.4s, v17.4s", "fcmgt v3.4s, v3.4s, v17.4s", "mov v16.16b, v3.16b", @@ -4440,7 +4440,7 @@ "Map 1 0b01 0xd0 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2432]", + "ldr q2, [x28, #2464]", "eor v2.16b, v18.16b, v2.16b", "fadd v16.2d, v17.2d, v2.2d" ] @@ -4463,7 +4463,7 @@ "Map 1 0b11 0xd0 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2400]", + "ldr q2, [x28, #2432]", "eor v2.16b, v18.16b, v2.16b", "fadd v16.4s, v17.4s, v2.4s" ] @@ -4600,7 +4600,7 @@ "Map 1 0b01 0xd7 256-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2656]", + "ldr q2, [x28, #2688]", "cmlt v3.16b, v16.16b, #0", "and v2.16b, v3.16b, v2.16b", "addp v2.16b, v2.16b, v2.16b", @@ -4992,8 +4992,8 @@ "Map 1 0b01 0xe6 128-bit" ], "ExpectedArm64ASM": [ - "ldr d2, [x28, #2880]", - "ldr q3, [x28, #2832]", + "ldr d2, [x28, #2912]", + "ldr q3, [x28, #2864]", "fcvtzs z4.s, p6/m, z17.d", "uzp1 z4.s, z4.s, z4.s", "mov v4.8b, v4.8b", @@ -5009,7 +5009,7 @@ "Map 1 0b01 0xe6 256-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2880]", + "ldr q2, [x28, #2912]", "ldr x0, [x28, #2000]", "ld1b {z3.b}, p7/z, [x0]", "fcvtzs z4.s, p7/m, z17.d", @@ -5053,8 +5053,8 @@ ], "ExpectedArm64ASM": [ "frinti v2.2d, v17.2d", - "ldr d3, [x28, #2880]", - "ldr q4, [x28, #2832]", + "ldr d3, [x28, #2912]", + "ldr q4, [x28, #2864]", "fcvtzs z5.s, p6/m, z2.d", "uzp1 z5.s, z5.s, z5.s", "mov v5.8b, v5.8b", @@ -5071,7 +5071,7 @@ ], "ExpectedArm64ASM": [ "frinti z2.d, p7/m, z17.d", - "ldr q3, [x28, #2880]", + "ldr q3, [x28, #2912]", "ldr x0, [x28, #2000]", "ld1b {z4.b}, p7/z, [x0]", "fcvtzs z5.s, p7/m, z2.d", diff --git a/unittests/InstructionCountCI/VEX_map2.json b/unittests/InstructionCountCI/VEX_map2.json index c2b7fcef19..fbe27087eb 100644 --- a/unittests/InstructionCountCI/VEX_map2.json +++ b/unittests/InstructionCountCI/VEX_map2.json @@ -1603,7 +1603,7 @@ "Map 2 0b01 0x41 256-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2368]", + "ldr q2, [x28, #2400]", "zip1 v3.8h, v2.8h, v17.8h", "zip2 v2.8h, v2.8h, v17.8h", "umin v2.4s, v3.4s, v2.4s", @@ -3657,7 +3657,7 @@ "Map 2 0b01 0x96 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2400]", + "ldr q2, [x28, #2432]", "eor v2.16b, v17.16b, v2.16b", "fmla v2.4s, v16.4s, v18.4s", "mov v16.16b, v2.16b" @@ -3683,7 +3683,7 @@ "Map 2 0b01 0x96 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2432]", + "ldr q2, [x28, #2464]", "eor v2.16b, v17.16b, v2.16b", "fmla v2.2d, v16.2d, v18.2d", "mov v16.16b, v2.16b" @@ -3709,7 +3709,7 @@ "Map 2 0b01 0x97 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2464]", + "ldr q2, [x28, #2496]", "eor v2.16b, v17.16b, v2.16b", "fmla v2.4s, v16.4s, v18.4s", "mov v16.16b, v2.16b" @@ -3735,7 +3735,7 @@ "Map 2 0b01 0x97 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2496]", + "ldr q2, [x28, #2528]", "eor v2.16b, v17.16b, v2.16b", "fmla v2.2d, v16.2d, v18.2d", "mov v16.16b, v2.16b" @@ -4609,7 +4609,7 @@ "Map 2 0b01 0xa6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2400]", + "ldr q2, [x28, #2432]", "eor v2.16b, v18.16b, v2.16b", "fmla v2.4s, v17.4s, v16.4s", "mov v16.16b, v2.16b" @@ -4635,7 +4635,7 @@ "Map 2 0b01 0xa6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2432]", + "ldr q2, [x28, #2464]", "eor v2.16b, v18.16b, v2.16b", "fmla v2.2d, v17.2d, v16.2d", "mov v16.16b, v2.16b" @@ -4661,7 +4661,7 @@ "Map 2 0b01 0xa7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2464]", + "ldr q2, [x28, #2496]", "eor v2.16b, v18.16b, v2.16b", "fmla v2.4s, v17.4s, v16.4s", "mov v16.16b, v2.16b" @@ -4687,7 +4687,7 @@ "Map 2 0b01 0xa7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2496]", + "ldr q2, [x28, #2528]", "eor v2.16b, v18.16b, v2.16b", "fmla v2.2d, v17.2d, v16.2d", "mov v16.16b, v2.16b" @@ -4713,7 +4713,7 @@ "Map 2 0b01 0xb6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2400]", + "ldr q2, [x28, #2432]", "eor v2.16b, v16.16b, v2.16b", "fmla v2.4s, v17.4s, v18.4s", "mov v16.16b, v2.16b" @@ -4738,7 +4738,7 @@ "Map 2 0b01 0xb6 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2432]", + "ldr q2, [x28, #2464]", "eor v2.16b, v16.16b, v2.16b", "fmla v2.2d, v17.2d, v18.2d", "mov v16.16b, v2.16b" @@ -4763,7 +4763,7 @@ "Map 2 0b01 0xb7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2464]", + "ldr q2, [x28, #2496]", "eor v2.16b, v16.16b, v2.16b", "fmla v2.4s, v17.4s, v18.4s", "mov v16.16b, v2.16b" @@ -4788,7 +4788,7 @@ "Map 2 0b01 0xb7 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2496]", + "ldr q2, [x28, #2528]", "eor v2.16b, v16.16b, v2.16b", "fmla v2.2d, v17.2d, v18.2d", "mov v16.16b, v2.16b" diff --git a/unittests/InstructionCountCI/VEX_map3.json b/unittests/InstructionCountCI/VEX_map3.json index 667ad01881..7f3a344aaf 100644 --- a/unittests/InstructionCountCI/VEX_map3.json +++ b/unittests/InstructionCountCI/VEX_map3.json @@ -5372,7 +5372,7 @@ "Map 3 0b01 0xdf 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2544]", + "ldr q2, [x28, #2576]", "movi v3.2d, #0x0", "mov v16.16b, v17.16b", "unimplemented (Unimplemented)", @@ -5385,7 +5385,7 @@ "Map 3 0b01 0xdf 128-bit" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2544]", + "ldr q2, [x28, #2576]", "movi v3.2d, #0x0", "mov v16.16b, v17.16b", "unimplemented (Unimplemented)", diff --git a/unittests/InstructionCountCI/x87.json b/unittests/InstructionCountCI/x87.json index 02d37281d1..54e97fa66d 100644 --- a/unittests/InstructionCountCI/x87.json +++ b/unittests/InstructionCountCI/x87.json @@ -4171,7 +4171,7 @@ "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "ldr q3, [x28, #2912]", + "ldr q3, [x28, #2944]", "eor v2.16b, v2.16b, v3.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" @@ -4186,7 +4186,7 @@ "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q2, [x0, #1040]", - "ldr q3, [x28, #2912]", + "ldr q3, [x28, #2944]", "bic v2.16b, v2.16b, v3.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]" @@ -4271,7 +4271,7 @@ "0xd9 11b 0xe8 /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2688]", + "ldr q2, [x28, #2720]", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", @@ -4291,7 +4291,7 @@ "0xd9 11b 0xe9 /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2704]", + "ldr q2, [x28, #2736]", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", @@ -4311,7 +4311,7 @@ "0xd9 11b 0xea /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2720]", + "ldr q2, [x28, #2752]", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", @@ -4331,7 +4331,7 @@ "0xd9 11b 0xeb /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2736]", + "ldr q2, [x28, #2768]", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", @@ -4351,7 +4351,7 @@ "0xd9 11b 0xec /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2752]", + "ldr q2, [x28, #2784]", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", @@ -4371,7 +4371,7 @@ "0xd9 11b 0xed /5" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2768]", + "ldr q2, [x28, #2800]", "ldrb w20, [x28, #1019]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", @@ -4528,7 +4528,7 @@ "mov v2.16b, v0.16b", "add x0, x28, x20, lsl #4", "str q2, [x0, #1040]", - "ldr q2, [x28, #2688]", + "ldr q2, [x28, #2720]", "mov w21, #0x1", "sub w20, w20, #0x1 (1)", "and w20, w20, #0x7", @@ -4798,7 +4798,7 @@ "0xd9 11b 0xf9 /7" ], "ExpectedArm64ASM": [ - "ldr q2, [x28, #2688]", + "ldr q2, [x28, #2720]", "ldrb w20, [x28, #1019]", "add x0, x28, x20, lsl #4", "ldr q3, [x0, #1040]",