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InstcountCI: Update
1 parent 5b4fd59 commit 6728055

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5 files changed

+149
-177
lines changed

5 files changed

+149
-177
lines changed

unittests/InstructionCountCI/FEXOpt/MultiInst_TSO.json

+12-22
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,7 @@
2121
"Instructions": {
2222
"Load variables from memory": {
2323
"x86InstructionCount": 6,
24-
"ExpectedInstructionCount": 18,
24+
"ExpectedInstructionCount": 13,
2525
"Comment": [
2626
"Just to ensure small atomic offset loads are using LRCPC2"
2727
],
@@ -36,27 +36,22 @@
3636
"ExpectedArm64ASM": [
3737
"ldapur w11, [x7]",
3838
"nop",
39-
"add x20, x7, #0x4 (4)",
40-
"ldapur w5, [x20]",
39+
"ldapur w5, [x7, #4]",
4140
"nop",
42-
"add x20, x7, #0x8 (8)",
43-
"ldapur x6, [x20]",
41+
"ldapur x6, [x7, #8]",
4442
"nop",
45-
"add x20, x7, #0x10 (16)",
46-
"ldapur x10, [x20]",
43+
"ldapur x10, [x7, #16]",
4744
"nop",
48-
"add x20, x7, #0x18 (24)",
49-
"ldapurh w20, [x20]",
45+
"ldapurh w20, [x7, #24]",
5046
"nop",
5147
"bfxil x4, x20, #0, #16",
52-
"add x20, x7, #0x1a (26)",
53-
"ldapurb w20, [x20]",
48+
"ldapurb w20, [x7, #26]",
5449
"bfxil x6, x20, #0, #8"
5550
]
5651
},
5752
"Store variables to memory": {
5853
"x86InstructionCount": 6,
59-
"ExpectedInstructionCount": 16,
54+
"ExpectedInstructionCount": 11,
6055
"Comment": [
6156
"Just to ensure small atomic offset stores are using LRCPC2"
6257
],
@@ -71,20 +66,15 @@
7166
"ExpectedArm64ASM": [
7267
"nop",
7368
"stlur w11, [x7]",
74-
"add x20, x7, #0x4 (4)",
7569
"nop",
76-
"stlur w5, [x20]",
77-
"add x20, x7, #0x8 (8)",
70+
"stlur w5, [x7, #4]",
7871
"nop",
79-
"stlur x6, [x20]",
80-
"add x20, x7, #0x10 (16)",
72+
"stlur x6, [x7, #8]",
8173
"nop",
82-
"stlur x10, [x20]",
83-
"add x20, x7, #0x18 (24)",
74+
"stlur x10, [x7, #16]",
8475
"nop",
85-
"stlurh w4, [x20]",
86-
"add x20, x7, #0x1a (26)",
87-
"stlurb w6, [x20]"
76+
"stlurh w4, [x7, #24]",
77+
"stlurb w6, [x7, #26]"
8878
]
8979
}
9080
}

unittests/InstructionCountCI/FEXOpt/MultiInst_TSO_32bit.json

+14-25
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,7 @@
2121
"Instructions": {
2222
"Load variables from structs": {
2323
"x86InstructionCount": 7,
24-
"ExpectedInstructionCount": 21,
24+
"ExpectedInstructionCount": 16,
2525
"Comment": [
2626
"Saw this in 32-bit libvulkan_freedreno.so:tu_cs_begin_sub_stream_aligned",
2727
"Loads a bunch of values from structs passed as arguments",
@@ -37,23 +37,18 @@
3737
"sub eax, [ebx + 4]"
3838
],
3939
"ExpectedArm64ASM": [
40-
"add w20, w7, #0x8 (8)",
41-
"ldapur w11, [x20]",
40+
"ldapur w11, [x7, #8]",
4241
"nop",
43-
"add w20, w7, #0x4 (4)",
44-
"ldapur w5, [x20]",
42+
"ldapur w5, [x7, #4]",
4543
"nop",
4644
"ldapur w6, [x7]",
4745
"nop",
48-
"add w20, w7, #0xc (12)",
49-
"ldapur w10, [x20]",
46+
"ldapur w10, [x7, #12]",
5047
"nop",
5148
"mul w5, w5, w11",
52-
"add w20, w6, #0xc (12)",
53-
"ldapur w4, [x20]",
49+
"ldapur w4, [x6, #12]",
5450
"nop",
55-
"add w20, w6, #0x4 (4)",
56-
"ldapur w20, [x20]",
51+
"ldapur w20, [x6, #4]",
5752
"nop",
5853
"eor x27, x4, x20",
5954
"subs w26, w4, w20",
@@ -62,7 +57,7 @@
6257
},
6358
"Load variables from memory": {
6459
"x86InstructionCount": 4,
65-
"ExpectedInstructionCount": 12,
60+
"ExpectedInstructionCount": 9,
6661
"Comment": [
6762
"Just to ensure small atomic offset loads are using LRCPC2"
6863
],
@@ -75,21 +70,18 @@
7570
"ExpectedArm64ASM": [
7671
"ldapur w11, [x7]",
7772
"nop",
78-
"add w20, w7, #0x4 (4)",
79-
"ldapur w5, [x20]",
73+
"ldapur w5, [x7, #4]",
8074
"nop",
81-
"add w20, w7, #0x18 (24)",
82-
"ldapurh w20, [x20]",
75+
"ldapurh w20, [x7, #24]",
8376
"nop",
8477
"bfxil w4, w20, #0, #16",
85-
"add w20, w7, #0x1a (26)",
86-
"ldapurb w20, [x20]",
78+
"ldapurb w20, [x7, #26]",
8779
"bfxil w6, w20, #0, #8"
8880
]
8981
},
9082
"Store variables to memory": {
9183
"x86InstructionCount": 4,
92-
"ExpectedInstructionCount": 10,
84+
"ExpectedInstructionCount": 7,
9385
"Comment": [
9486
"Just to ensure small atomic offset stores are using LRCPC2"
9587
],
@@ -102,14 +94,11 @@
10294
"ExpectedArm64ASM": [
10395
"nop",
10496
"stlur w11, [x7]",
105-
"add w20, w7, #0x4 (4)",
10697
"nop",
107-
"stlur w5, [x20]",
108-
"add w20, w7, #0x18 (24)",
98+
"stlur w5, [x7, #4]",
10999
"nop",
110-
"stlurh w4, [x20]",
111-
"add w20, w7, #0x1a (26)",
112-
"stlurb w6, [x20]"
100+
"stlurh w4, [x7, #24]",
101+
"stlurb w6, [x7, #26]"
113102
]
114103
}
115104
}

unittests/InstructionCountCI/FlagM/HotBlocks_TSO_32Bit.json

+8-15
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@
1717
"Instructions": {
1818
"The Sims 1 hot block": {
1919
"x86InstructionCount": 47,
20-
"ExpectedInstructionCount": 105,
20+
"ExpectedInstructionCount": 98,
2121
"Comment": [
2222
"Hottest in-game block from The Sims 1, Legacy Collection",
2323
"Consumed 6.13% of a CPU core on Oryon-1",
@@ -88,16 +88,13 @@
8888
"ldapur w4, [x20]",
8989
"nop",
9090
"eor w4, w4, w9",
91-
"sub w20, w9, #0x4 (4)",
9291
"nop",
93-
"stlur w4, [x20]",
94-
"add w20, w9, #0x8 (8)",
95-
"ldapur w5, [x20]",
92+
"stlur w4, [x9, #-4]",
93+
"ldapur w5, [x9, #8]",
9694
"nop",
9795
"str w6, [x8, #-4]!",
9896
"str w10, [x8, #-4]!",
99-
"add w20, w9, #0x18 (24)",
100-
"ldapur w10, [x20]",
97+
"ldapur w10, [x9, #24]",
10198
"nop",
10299
"str w11, [x8, #-4]!",
103100
"mov x11, x7",
@@ -117,28 +114,24 @@
117114
"sub w20, w9, #0x188 (392)",
118115
"nop",
119116
"stlur w4, [x20]",
120-
"add w20, w9, #0xc (12)",
121-
"ldapur w4, [x20]",
117+
"ldapur w4, [x9, #12]",
122118
"nop",
123119
"sub w20, w9, #0x178 (376)",
124120
"nop",
125121
"stlur w4, [x20]",
126-
"add w20, w9, #0x10 (16)",
127-
"ldapur w4, [x20]",
122+
"ldapur w4, [x9, #16]",
128123
"nop",
129124
"sub w20, w9, #0x170 (368)",
130125
"nop",
131126
"stlur w4, [x20]",
132-
"add w20, w9, #0x14 (20)",
133-
"ldapurb w4, [x20]",
127+
"ldapurb w4, [x9, #20]",
134128
"sub w20, w9, #0x17c (380)",
135129
"nop",
136130
"stlur w4, [x20]",
137131
"ldur d16, [x10, #-40]",
138132
"dmb ishld",
139133
"movi v17.2d, #0x0",
140-
"sub w20, w10, #0x20 (32)",
141-
"ldapur w4, [x20]",
134+
"ldapur w4, [x10, #-32]",
142135
"nop",
143136
"add w10, w10, #0x4c (76)",
144137
"mov x20, #0xfffffffffffffe3c",

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