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Copy pathgalaga_tangnano20k.gprj
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galaga_tangnano20k.gprj
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<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE gowin-fpga-project>
<Project>
<Template>FPGA</Template>
<Version>5</Version>
<Device name="GW2AR-18C" pn="GW2AR-LV18QN88C8/I7">gw2ar18c-000</Device>
<FileList>
<File path="src/gowin_clkdiv/gowin_clkdiv.v" type="file.verilog" enable="1"/>
<File path="../mist/scandoubler.v" type="file.verilog" enable="1"/>
<File path="src/gowin_rpll/gowin_rpll.v" type="file.verilog" enable="1"/>
<File path="src/hdmi2/audio_clock_regeneration_packet.sv" type="file.verilog" enable="1"/>
<File path="src/hdmi2/audio_info_frame.sv" type="file.verilog" enable="1"/>
<File path="src/hdmi2/audio_sample_packet.sv" type="file.verilog" enable="1"/>
<File path="src/hdmi2/auxiliary_video_information_info_frame.sv" type="file.verilog" enable="1"/>
<File path="src/hdmi2/hdmi.sv" type="file.verilog" enable="1"/>
<File path="src/hdmi2/packet_assembler.sv" type="file.verilog" enable="1"/>
<File path="src/hdmi2/packet_picker.sv" type="file.verilog" enable="1"/>
<File path="src/hdmi2/serializer.sv" type="file.verilog" enable="1"/>
<File path="src/hdmi2/source_product_description_info_frame.sv" type="file.verilog" enable="1"/>
<File path="src/hdmi2/tmds_channel.sv" type="file.verilog" enable="1"/>
<File path="../rtl_T80/T80.vhd" type="file.vhdl" enable="1"/>
<File path="../rtl_T80/T80_ALU.vhd" type="file.vhdl" enable="1"/>
<File path="../rtl_T80/T80_MCode.vhd" type="file.vhdl" enable="1"/>
<File path="../rtl_T80/T80_Pack.vhd" type="file.vhdl" enable="1"/>
<File path="../rtl_T80/T80_Reg.vhd" type="file.vhdl" enable="1"/>
<File path="../rtl_T80/T80se.vhd" type="file.vhdl" enable="1"/>
<File path="../rtl_dar/galaga.vhd" type="file.vhdl" enable="1"/>
<File path="../rtl_dar/gen_ram.vhd" type="file.vhdl" enable="1"/>
<File path="../rtl_dar/gen_video.vhd" type="file.vhdl" enable="1"/>
<File path="../rtl_dar/io_ps2_keyboard.vhd" type="file.vhdl" enable="1"/>
<File path="../rtl_dar/kbd_joystick.vhd" type="file.vhdl" enable="1"/>
<File path="../rtl_dar/mb88.vhd" type="file.vhdl" enable="1"/>
<File path="../rtl_dar/proms/bg_graphx.vhd" type="file.vhdl" enable="1"/>
<File path="../rtl_dar/proms/bg_palette.vhd" type="file.vhdl" enable="1"/>
<File path="../rtl_dar/proms/cs54xx_prog.vhd" type="file.vhdl" enable="1"/>
<File path="../rtl_dar/proms/galaga_cpu1.vhd" type="file.vhdl" enable="1"/>
<File path="../rtl_dar/proms/galaga_cpu2.vhd" type="file.vhdl" enable="1"/>
<File path="../rtl_dar/proms/galaga_cpu3.vhd" type="file.vhdl" enable="1"/>
<File path="../rtl_dar/proms/rgb.vhd" type="file.vhdl" enable="1"/>
<File path="../rtl_dar/proms/sound_samples.vhd" type="file.vhdl" enable="1"/>
<File path="../rtl_dar/proms/sound_seq.vhd" type="file.vhdl" enable="1"/>
<File path="../rtl_dar/proms/sp_graphx.vhd" type="file.vhdl" enable="1"/>
<File path="../rtl_dar/proms/sp_palette.vhd" type="file.vhdl" enable="1"/>
<File path="../rtl_dar/sound_machine.vhd" type="file.vhdl" enable="1"/>
<File path="../rtl_dar/stars.vhd" type="file.vhdl" enable="1"/>
<File path="../rtl_dar/stars_machine.vhd" type="file.vhdl" enable="1"/>
<File path="src/galaga_tangnano20k.vhd" type="file.vhdl" enable="1"/>
<File path="src/galaga_tangnano20k.cst" type="file.cst" enable="1"/>
<File path="src/dualshock_controller.v" type="file.verilog" enable="1"/>
</FileList>
</Project>