pfe_class_csr.t2t

== Class control and status registers (CLASS_CSR) ==[pfe_class_csr]

Various control and registers for all the Class PEs.

=== Class CSR registers ===[pfe_class_csr_regs]

|| Base offset in CBUS | Seen from ARM | Seen from any PE ||
| 0x00320000 | 0x9c320000 | 0xc0320000 |

Registers:

|| Offset | Symbol | Description ||
| 0x0000 | [VERSION #pfe_class_csr_reg_version] | Class PE version |
| 0x0004 | [TX_CTRL #pfe_class_csr_reg_tx_ctrl] | Class PE core control |
| 0x0010 | INQ_PKTPTR |  |
| 0x0014 | HDR_SIZE |  |
| 0x0020 | PE0_QB_DM_ADDR0 | DMEM address of 1st and 2nd buffers on QB side |
| 0x0024 | PE0_QB_DM_ADDR1 | DMEM address of 3rd and 4th buffers on QB side |
| 0x0060 | PE0_RO_DM_ADDR0 | DMEM address of 1st and 2nd buffers on RO side |
| 0x0064 | PE0_RO_DM_ADDR1 | DMEM address of 3rd and 4th buffers on RO side |
| 0x0100 | [MEM_ACCESS_ADDR #pfe_class_csr_reg_mem_access_addr] | Class PE memory access command/address register |
| 0x0104 | [MEM_ACCESS_WDATA #pfe_class_csr_reg_mem_access_wdata] | Data to write to Class PE memory |
| 0x0108 | [MEM_ACCESS_RDATA #pfe_class_csr_reg_mem_access_rdata] | Data read from Class PE memory |
| 0x0114 | TM_INQ_ADDR |  |
| 0x0118 | PE_STATUS |  |
| 0x011c | PHY1_RX_PKTS |  |
| 0x0120 | PHY1_TX_PKTS |  |
| 0x0124 | PHY1_LP_FAIL_PKTS |  |
| 0x0128 | PHY1_INTF_FAIL_PKTS |  |
| 0x012c | PHY1_INTF_MATCH_PKTS |  |
| 0x0130 | PHY1_L3_FAIL_PKTS |  |
| 0x0134 | PHY1_V4_PKTS |  |
| 0x0138 | PHY1_V6_PKTS |  |
| 0x013c | PHY1_CHKSUM_ERR_PKTS |  |
| 0x0140 | PHY1_TTL_ERR_PKTS |  |
| 0x0144 | PHY2_RX_PKTS |  |
| 0x0148 | PHY2_TX_PKTS |  |
| 0x014c | PHY2_LP_FAIL_PKTS |  |
| 0x0150 | PHY2_INTF_FAIL_PKTS |  |
| 0x0154 | PHY2_INTF_MATCH_PKTS |  |
| 0x0158 | PHY2_L3_FAIL_PKTS |  |
| 0x015c | PHY2_V4_PKTS |  |
| 0x0160 | PHY2_V6_PKTS |  |
| 0x0164 | PHY2_CHKSUM_ERR_PKTS |  |
| 0x0168 | PHY2_TTL_ERR_PKTS |  |
| 0x016c | PHY3_RX_PKTS |  |
| 0x0170 | PHY3_TX_PKTS |  |
| 0x0174 | PHY3_LP_FAIL_PKTS |  |
| 0x0178 | PHY3_INTF_FAIL_PKTS |  |
| 0x017c | PHY3_INTF_MATCH_PKTS |  |
| 0x0180 | PHY3_L3_FAIL_PKTS |  |
| 0x0184 | PHY3_V4_PKTS |  |
| 0x0188 | PHY3_V6_PKTS |  |
| 0x018c | PHY3_CHKSUM_ERR_PKTS |  |
| 0x0190 | PHY3_TTL_ERR_PKTS |  |
| 0x0194 | PHY1_ICMP_PKTS |  |
| 0x0198 | PHY1_IGMP_PKTS |  |
| 0x019c | PHY1_TCP_PKTS |  |
| 0x01a0 | PHY1_UDP_PKTS |  |
| 0x01a4 | PHY2_ICMP_PKTS |  |
| 0x01a8 | PHY2_IGMP_PKTS |  |
| 0x01ac | PHY2_TCP_PKTS |  |
| 0x01b0 | PHY2_UDP_PKTS |  |
| 0x01b4 | PHY3_ICMP_PKTS |  |
| 0x01b8 | PHY3_IGMP_PKTS |  |
| 0x01bc | PHY3_TCP_PKTS |  |
| 0x01c0 | PHY3_UDP_PKTS |  |
| 0x01c4 | PHY4_ICMP_PKTS |  |
| 0x01c8 | PHY4_IGMP_PKTS |  |
| 0x01cc | PHY4_TCP_PKTS |  |
| 0x01d0 | PHY4_UDP_PKTS |  |
| 0x01d4 | PHY4_RX_PKTS |  |
| 0x01d8 | PHY4_TX_PKTS |  |
| 0x01dc | PHY4_LP_FAIL_PKTS |  |
| 0x01e0 | PHY4_INTF_FAIL_PKTS |  |
| 0x01e4 | PHY4_INTF_MATCH_PKTS |  |
| 0x01e8 | PHY4_L3_FAIL_PKTS |  |
| 0x01ec | PHY4_V4_PKTS |  |
| 0x01f0 | PHY4_V6_PKTS |  |
| 0x01f4 | PHY4_CHKSUM_ERR_PKTS |  |
| 0x01f8 | PHY4_TTL_ERR_PKTS |  |
| 0x0200 | [PE_SYS_CLK_RATIO #pfe_class_csr_reg_pe_sys_clk_ratio] | Core clock/bus clock ratio |
| 0x0204 | AFULL_THRES |  |
| 0x0208 | GAP_BETWEEN_READS |  |
| 0x020c | MAX_BUF_CNT |  |
| 0x0210 | TSQ_FIFO_THRES |  |
| 0x0214 | TSQ_MAX_CNT |  |
| 0x0218 | IRAM_DATA_0 |  |
| 0x021c | IRAM_DATA_1 |  |
| 0x0220 | IRAM_DATA_2 |  |
| 0x0224 | IRAM_DATA_3 |  |
| 0x0228 | [BUS_ACCESS_ADDR #pfe_class_csr_reg_bus_access_addr] | Class bus access command/address register |
| 0x022c | [BUS_ACCESS_WDATA #pfe_class_csr_reg_bus_access_wdata] | Data to write to Class bus |
| 0x0230 | [BUS_ACCESS_RDATA #pfe_class_csr_reg_bus_access_rdata] | Data read from Class bus |
| 0x0234 | ROUTE_HASH_ENTRY_SIZE |  |
| 0x0238 | ROUTE_TABLE_BASE |  |
| 0x023c | [ROUTE_MULTI #pfe_class_csr_reg_route_multi] | Route table configuration |
| 0x0240 | SMEM_OFFSET |  |
| 0x0244 | LMEM_BUF_SIZE |  |
| 0x0248 | VLAN_ID |  |
| 0x024c | BMU1_BUF_FREE |  |
| 0x0250 | USE_TMU_INQ |  |
| 0x0254 | VLAN_ID1 |  |
| 0x0258 | [BUS_ACCESS_BASE #pfe_class_csr_reg_bus_access_base] | High byte of bus access address |
| 0x025c | [HIF_PARSE #pfe_class_csr_reg_hif_parse] |  |
| 0x0260 | HOST_PE0_GP | Host general purpose register for PE0 |
| 0x0264 | PE0_GP | PE general purpose register for PE0 |
| 0x0268 | HOST_PE1_GP | Host general purpose register for PE1 |
| 0x026c | PE1_GP | PE general purpose register for PE1 |
| 0x0270 | HOST_PE2_GP | Host general purpose register for PE2 |
| 0x0274 | PE2_GP | PE general purpose register for PE2 |
| 0x0278 | HOST_PE3_GP | Host general purpose register for PE3 |
| 0x027c | PE3_GP | PE general purpose register for PE3 |
| 0x0280 | HOST_PE4_GP | Host general purpose register for PE4 |
| 0x0284 | PE4_GP | PE general purpose register for PE4 |
| 0x0288 | HOST_PE5_GP | Host general purpose register for PE5 |
| 0x028c | PE5_GP | PE general purpose register for PE5 |
| 0x0290 | PE_INT_SRC |  |
| 0x0294 | PE_INT_ENABLE |  |
| 0x0298 | TPID0_TPID1 |  |
| 0x029c | TPID2 |  |
| 0x02a0 | [L4_CHKSUM_ADDR #pfe_class_csr_reg_l4_chksum_addr] |  |
| 0x02a4 | PE0_DEBUG |  |
| 0x02a8 | PE1_DEBUG |  |
| 0x02ac | PE2_DEBUG |  |
| 0x02b0 | PE3_DEBUG |  |
| 0x02b4 | PE4_DEBUG |  |
| 0x02b8 | PE5_DEBUG |  |
| 0x02bc | STATE |  |

==== VERSION (0x0000) ====[pfe_class_csr_reg_version]

Class PE block version

|| Symbol | Bit range | R/W | Description ||
| VERSION | 31-0 | R | Class PE block version. (0x20) |

==== TX_CTRL (0x0004) ====[pfe_class_csr_reg_tx_ctrl]

Class PE core state control.

|| Symbol | Bit range | R/W | Description ||
| CTRL | 1-0 | RW | Enable/reset PE cores. 0=disable 1=enable 2=software reset |

==== MEM_ACCESS_ADDR (0x0100) ====[pfe_class_csr_reg_mem_access_addr]

Class PE internal memory access command/address register.

This register allows indirect access to a PE's internal memory. Writing a
command into this register will trigger a read or write operation at the
requested address.

IMEM is only accessible when the Class cores are disabled
([TX_CTRL #pfe_class_csr_reg_tx_ctrl] set to 0). DMEM is always accessible.

Warning: The PFE core clock must be enabled using the
[PFE_CLK_CNTRL #peri_clkcore_regs] register prior performing indirect memory
access using this register, otherwise the transaction will hang.

|| Symbol | Bit range | R/W | Description ||
| csr_pe_mem_cmd | 31 | RW | Read or write command. 0=read 1=write |
| csr_pe_mem_wren | 27-24 | RW | Bit mask indicating which data bytes will be read/written, interpreted in big endian. |
| csr_pe_mem_addr | 23-0 | RW | PE memory address to read/write. Address should be on a word boundary. |

csr_pe_mem_addr decoding:

|| Base offset | PE | Memory type | Size ||
| 0x008000 | CLASS0 | IMEM | 0x8000 |
| 0x010000 | CLASS0 | DMEM | 0x2000 |
| 0x108000 | CLASS1 | IMEM | 0x8000 |
| 0x110000 | CLASS1 | DMEM | 0x2000 |
| 0x208000 | CLASS2 | IMEM | 0x8000 |
| 0x210000 | CLASS2 | DMEM | 0x2000 |
| 0x308000 | CLASS3 | IMEM | 0x8000 |
| 0x310000 | CLASS3 | DMEM | 0x2000 |
| 0x408000 | CLASS4 | IMEM | 0x8000 |
| 0x410000 | CLASS4 | DMEM | 0x2000 |
| 0x508000 | CLASS5 | IMEM | 0x8000 |
| 0x510000 | CLASS5 | DMEM | 0x2000 |

==== MEM_ACCESS_WDATA (0x0104) ====[pfe_class_csr_reg_mem_access_wdata]

Class PE internal memory write data register. Contains the data to write when
a write request is written into
[MEM_ACCESS_ADDR #pfe_class_csr_reg_mem_access_addr]. Value is in big endian.

|| Symbol | Bit range | R/W | Description ||
| WDATA | 31-0 | RW | Word to write into internal memory |

==== MEM_ACCESS_RDATA (0x0108) ====[pfe_class_csr_reg_mem_access_rdata]

Class PE internal memory read data register. Contains the data read after
writing a read request into
[MEM_ACCESS_ADDR #pfe_class_csr_reg_mem_access_addr]. Value is in big endian.

|| Symbol | Bit range | R/W | Description ||
| RDATA | 31-0 | RW | Word read from internal memory |

==== PE_SYS_CLK_RATIO (0x0200) ====[pfe_class_csr_reg_pe_sys_clk_ratio]

Core clock/bus clock ratio.

|| Symbol | Bit range | R/W | Description ||
| RATIO | 1-0 | RW | Core clock/system bus clock ratio. 0=1:1 1=2:1 |

==== BUS_ACCESS_ADDR (0x0228) ====[pfe_class_csr_reg_bus_access_addr]

Class PE internal bus access command/address register.

This register allows indirect access to the Class bus. Writing a command into
this register will trigger a read or write operation at the requested address.

|| Symbol | Bit range | R/W | Description ||
| CMD | 31 | RW | Read of write command. 0=read 1=write |
| WIDTH | 27-24 | RW | Access width in bytes. 1=byte 2=hword 4=word. |
| ADDR | 23-0 | RW | Class bus address where the access will be performed. Bits 31-24 are stored in [BUS_ACCESS_BASE #pfe_class_csr_reg_bus_access_base]. |

==== BUS_ACCESS_WDATA (0x022c) ====[pfe_class_csr_reg_bus_access_wdata]

Data word to write during Class bus access write request started by a write
in [BUS_ACCESS_ADDR #pfe_class_csr_reg_bus_access_addr]. Value is in big
endian.

|| Symbol | Bit range | R/W | Description ||
| WDATA | 31-0 | RW | Word to write to Class bus. Big endian. |

==== BUS_ACCESS_RDATA (0x0230) ====[pfe_class_csr_reg_bus_access_rdata]

Data word read after a Class bus access read request started by a write
in [BUS_ACCESS_ADDR #pfe_class_csr_reg_bus_access_addr]. Value is in big
endian.

|| Symbol | Bit range | R/W | Description ||
| RDATA | 31-0 | RW | Word read from Class bus. Big endian. |

==== ROUTE_MULTI (0x023c) ====[pfe_class_csr_reg_route_multi]

Route table configuration.

|| Symbol | Bit range | R/W | Description ||
| QB2BUS_LE | 15 | RW | Byte swap something? |
| HASH_TYPE | 13-12 | RW | Hash type: 0=normal 1=CRC port 2=CRC IP 3=CRC port+IP |
| CLASS_TOE | 11 | RW | ? |
| ARC_HIT_CHECK_EN | 7 | RW | ? |
| IP_ALIGNED | 6 | RW | ? |
| HW_BRIDGE_FETCH | 5 | RW | ? |
| HW_ROUTE_FETCH | 3 | RW | ? |
| PHYNO_IN_HASH | 1 | RW | Include PHY number in hash? |
| TWO_LEVEL_ROUTE | 0 | RW | ? |

==== BUS_ACCESS_BASE (0x0258) ====[pfe_class_csr_reg_bus_access_base]

|| Symbol | Bit range | R/W | Description ||
| BASE | 31-24 | RW | High byte of bus address used in indirect Class bus accesses |

==== HIF_PARSE (0x025c) ====[pfe_class_csr_reg_hif_parse]

|| Symbol | Bit range | R/W | Description ||
| HIF_PKT_OFFST | 4-1 | RW | Offset of HIF metadata in packet? |
| HIF_PKT_CLASS_EN | 0 | RW | Enable interpretation of HIF metadata? |


==== L4_CHKSUM_ADDR (0x02a0) ====[pfe_class_csr_reg_l4_chksum_addr]

|| Symbol | Bit range | R/W | Description ||
| IPV4_CHKSUM_DROP | 9 | RW | ? |
| UDP_CHKSUM_DROP | 1 | RW | ? |
| TCP_CHKSUM_DROP | 0 | RW | ? |